//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// The confidential and proprietary information contained in this file may     
// only be used by a person authorised under and to the extent permitted       
// by a subsisting licensing agreement from ARM Limited.                       
//                                                                             
//            (C) COPYRIGHT 2005-2013 ARM Limited.
//                ALL RIGHTS RESERVED                                          
//                                                                             
// This entire notice must be reproduced on all copies of this file            
// and copies of this file may only be made by a person if such person is      
// permitted to do so under the terms of a subsisting license agreement        
// from ARM Limited.                                                           
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Top-Level Verilog file is auto-generated by AMBA Designer ADr3p4-00rel0-build-0086
//                                                                             
// Stitcher: generic_stitcher_core v3.1, built on Sep 18 2013
//                                                                             
// Filename: nic400_cd_clk_core_200_800m_ysyx_rv32.v
// Created : Mon May 27 20:11:37 2024                            
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Generated with Validator version0.1


//-----------------------------------------------------------------------------
// Module Declaration nic400_cd_clk_core_200_800m_ysyx_rv32
//-----------------------------------------------------------------------------

module nic400_cd_clk_core_200_800m_ysyx_rv32 (
  
// Instance: u_amib_dma_axi4_cpu, Port: dma_axi4_cpu_m

  awid_dma_axi4_cpu_m,
  awaddr_dma_axi4_cpu_m,
  awlen_dma_axi4_cpu_m,
  awsize_dma_axi4_cpu_m,
  awburst_dma_axi4_cpu_m,
  awlock_dma_axi4_cpu_m,
  awcache_dma_axi4_cpu_m,
  awprot_dma_axi4_cpu_m,
  awvalid_dma_axi4_cpu_m,
  awready_dma_axi4_cpu_m,
  wdata_dma_axi4_cpu_m,
  wstrb_dma_axi4_cpu_m,
  wlast_dma_axi4_cpu_m,
  wvalid_dma_axi4_cpu_m,
  wready_dma_axi4_cpu_m,
  bid_dma_axi4_cpu_m,
  bresp_dma_axi4_cpu_m,
  bvalid_dma_axi4_cpu_m,
  bready_dma_axi4_cpu_m,
  arid_dma_axi4_cpu_m,
  araddr_dma_axi4_cpu_m,
  arlen_dma_axi4_cpu_m,
  arsize_dma_axi4_cpu_m,
  arburst_dma_axi4_cpu_m,
  arlock_dma_axi4_cpu_m,
  arcache_dma_axi4_cpu_m,
  arprot_dma_axi4_cpu_m,
  arvalid_dma_axi4_cpu_m,
  arready_dma_axi4_cpu_m,
  rid_dma_axi4_cpu_m,
  rdata_dma_axi4_cpu_m,
  rresp_dma_axi4_cpu_m,
  rlast_dma_axi4_cpu_m,
  rvalid_dma_axi4_cpu_m,
  rready_dma_axi4_cpu_m,
  
// Instance: u_amib_sram_slv_axi4, Port: sram_slv_axi4_m

  awid_sram_slv_axi4,
  awaddr_sram_slv_axi4,
  awlen_sram_slv_axi4,
  awsize_sram_slv_axi4,
  awburst_sram_slv_axi4,
  awlock_sram_slv_axi4,
  awcache_sram_slv_axi4,
  awprot_sram_slv_axi4,
  awvalid_sram_slv_axi4,
  awready_sram_slv_axi4,
  wdata_sram_slv_axi4,
  wstrb_sram_slv_axi4,
  wlast_sram_slv_axi4,
  wvalid_sram_slv_axi4,
  wready_sram_slv_axi4,
  bid_sram_slv_axi4,
  bresp_sram_slv_axi4,
  bvalid_sram_slv_axi4,
  bready_sram_slv_axi4,
  arid_sram_slv_axi4,
  araddr_sram_slv_axi4,
  arlen_sram_slv_axi4,
  arsize_sram_slv_axi4,
  arburst_sram_slv_axi4,
  arlock_sram_slv_axi4,
  arcache_sram_slv_axi4,
  arprot_sram_slv_axi4,
  arvalid_sram_slv_axi4,
  arready_sram_slv_axi4,
  rid_sram_slv_axi4,
  rdata_sram_slv_axi4,
  rresp_sram_slv_axi4,
  rlast_sram_slv_axi4,
  rvalid_sram_slv_axi4,
  rready_sram_slv_axi4,
  
// Instance: u_asib_cpu_mst_axi4, Port: cpu_mst_axi4_s

  awid_cpu_mst_axi4,
  awaddr_cpu_mst_axi4,
  awlen_cpu_mst_axi4,
  awsize_cpu_mst_axi4,
  awburst_cpu_mst_axi4,
  awlock_cpu_mst_axi4,
  awcache_cpu_mst_axi4,
  awprot_cpu_mst_axi4,
  awvalid_cpu_mst_axi4,
  awready_cpu_mst_axi4,
  wdata_cpu_mst_axi4,
  wstrb_cpu_mst_axi4,
  wlast_cpu_mst_axi4,
  wvalid_cpu_mst_axi4,
  wready_cpu_mst_axi4,
  bid_cpu_mst_axi4,
  bresp_cpu_mst_axi4,
  bvalid_cpu_mst_axi4,
  bready_cpu_mst_axi4,
  arid_cpu_mst_axi4,
  araddr_cpu_mst_axi4,
  arlen_cpu_mst_axi4,
  arsize_cpu_mst_axi4,
  arburst_cpu_mst_axi4,
  arlock_cpu_mst_axi4,
  arcache_cpu_mst_axi4,
  arprot_cpu_mst_axi4,
  arvalid_cpu_mst_axi4,
  arready_cpu_mst_axi4,
  rid_cpu_mst_axi4,
  rdata_cpu_mst_axi4,
  rresp_cpu_mst_axi4,
  rlast_cpu_mst_axi4,
  rvalid_cpu_mst_axi4,
  rready_cpu_mst_axi4,
  
// Instance: u_ib_chiplink_slv_axi4_tpv_ib_s, Port: chiplink_slv_axi4_tpv_ib_m_async

  aw_data_chiplink_slv_axi4_tpv_ib_int_async,
  aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async,
  aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  b_data_chiplink_slv_axi4_tpv_ib_int_async,
  b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async,
  b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  ar_data_chiplink_slv_axi4_tpv_ib_int_async,
  ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async,
  ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  r_data_chiplink_slv_axi4_tpv_ib_int_async,
  r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async,
  r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  w_data_chiplink_slv_axi4_tpv_ib_int_async,
  w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async,
  w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async,
  
// Instance: u_ib_dma_axi4_cpu_ib_m, Port: dma_axi4_cpu_ib_s_async

  aw_data_dma_axi4_cpu_ib_int_async,
  aw_rpntr_gry_dma_axi4_cpu_ib_int_async,
  aw_rpntr_bin_dma_axi4_cpu_ib_int_async,
  aw_wpntr_gry_dma_axi4_cpu_ib_int_async,
  b_data_dma_axi4_cpu_ib_int_async,
  b_rpntr_gry_dma_axi4_cpu_ib_int_async,
  b_rpntr_bin_dma_axi4_cpu_ib_int_async,
  b_wpntr_gry_dma_axi4_cpu_ib_int_async,
  ar_data_dma_axi4_cpu_ib_int_async,
  ar_rpntr_gry_dma_axi4_cpu_ib_int_async,
  ar_rpntr_bin_dma_axi4_cpu_ib_int_async,
  ar_wpntr_gry_dma_axi4_cpu_ib_int_async,
  r_data_dma_axi4_cpu_ib_int_async,
  r_rpntr_gry_dma_axi4_cpu_ib_int_async,
  r_rpntr_bin_dma_axi4_cpu_ib_int_async,
  r_wpntr_gry_dma_axi4_cpu_ib_int_async,
  w_data_dma_axi4_cpu_ib_int_async,
  w_rpntr_gry_dma_axi4_cpu_ib_int_async,
  w_rpntr_bin_dma_axi4_cpu_ib_int_async,
  w_wpntr_gry_dma_axi4_cpu_ib_int_async,
  
// Instance: u_ib_perip0_gp_apb4_ib_s, Port: perip0_gp_apb4_ib_m_async

  a_data_perip0_gp_apb4_ib_int_async,
  a_rpntr_gry_perip0_gp_apb4_ib_int_async,
  a_rpntr_bin_perip0_gp_apb4_ib_int_async,
  a_wpntr_gry_perip0_gp_apb4_ib_int_async,
  d_data_perip0_gp_apb4_ib_int_async,
  d_rpntr_gry_perip0_gp_apb4_ib_int_async,
  d_rpntr_bin_perip0_gp_apb4_ib_int_async,
  d_wpntr_gry_perip0_gp_apb4_ib_int_async,
  w_data_perip0_gp_apb4_ib_int_async,
  w_rpntr_gry_perip0_gp_apb4_ib_int_async,
  w_rpntr_bin_perip0_gp_apb4_ib_int_async,
  w_wpntr_gry_perip0_gp_apb4_ib_int_async,
  
// Instance: u_ib_perip1_gp_apb4_ib_s, Port: perip1_gp_apb4_ib_m_async

  a_data_perip1_gp_apb4_ib_int_async,
  a_rpntr_gry_perip1_gp_apb4_ib_int_async,
  a_rpntr_bin_perip1_gp_apb4_ib_int_async,
  a_wpntr_gry_perip1_gp_apb4_ib_int_async,
  d_data_perip1_gp_apb4_ib_int_async,
  d_rpntr_gry_perip1_gp_apb4_ib_int_async,
  d_rpntr_bin_perip1_gp_apb4_ib_int_async,
  d_wpntr_gry_perip1_gp_apb4_ib_int_async,
  w_data_perip1_gp_apb4_ib_int_async,
  w_rpntr_gry_perip1_gp_apb4_ib_int_async,
  w_rpntr_bin_perip1_gp_apb4_ib_int_async,
  w_wpntr_gry_perip1_gp_apb4_ib_int_async,
  
// Instance: u_ib_psram_slv_axi4_ib_s, Port: psram_slv_axi4_ib_m_async

  aw_data_psram_slv_axi4_ib_int_async,
  aw_rpntr_gry_psram_slv_axi4_ib_int_async,
  aw_rpntr_bin_psram_slv_axi4_ib_int_async,
  aw_wpntr_gry_psram_slv_axi4_ib_int_async,
  b_data_psram_slv_axi4_ib_int_async,
  b_rpntr_gry_psram_slv_axi4_ib_int_async,
  b_rpntr_bin_psram_slv_axi4_ib_int_async,
  b_wpntr_gry_psram_slv_axi4_ib_int_async,
  ar_data_psram_slv_axi4_ib_int_async,
  ar_rpntr_gry_psram_slv_axi4_ib_int_async,
  ar_rpntr_bin_psram_slv_axi4_ib_int_async,
  ar_wpntr_gry_psram_slv_axi4_ib_int_async,
  r_data_psram_slv_axi4_ib_int_async,
  r_rpntr_gry_psram_slv_axi4_ib_int_async,
  r_rpntr_bin_psram_slv_axi4_ib_int_async,
  r_wpntr_gry_psram_slv_axi4_ib_int_async,
  w_data_psram_slv_axi4_ib_int_async,
  w_rpntr_gry_psram_slv_axi4_ib_int_async,
  w_rpntr_bin_psram_slv_axi4_ib_int_async,
  w_wpntr_gry_psram_slv_axi4_ib_int_async,
  
// Instance: u_ib_sdram_slv_axi4_ib_s, Port: sdram_slv_axi4_ib_m_async

  aw_data_sdram_slv_axi4_ib_int_async,
  aw_rpntr_gry_sdram_slv_axi4_ib_int_async,
  aw_rpntr_bin_sdram_slv_axi4_ib_int_async,
  aw_wpntr_gry_sdram_slv_axi4_ib_int_async,
  b_data_sdram_slv_axi4_ib_int_async,
  b_rpntr_gry_sdram_slv_axi4_ib_int_async,
  b_rpntr_bin_sdram_slv_axi4_ib_int_async,
  b_wpntr_gry_sdram_slv_axi4_ib_int_async,
  ar_data_sdram_slv_axi4_ib_int_async,
  ar_rpntr_gry_sdram_slv_axi4_ib_int_async,
  ar_rpntr_bin_sdram_slv_axi4_ib_int_async,
  ar_wpntr_gry_sdram_slv_axi4_ib_int_async,
  r_data_sdram_slv_axi4_ib_int_async,
  r_rpntr_gry_sdram_slv_axi4_ib_int_async,
  r_rpntr_bin_sdram_slv_axi4_ib_int_async,
  r_wpntr_gry_sdram_slv_axi4_ib_int_async,
  w_data_sdram_slv_axi4_ib_int_async,
  w_rpntr_gry_sdram_slv_axi4_ib_int_async,
  w_rpntr_bin_sdram_slv_axi4_ib_int_async,
  w_wpntr_gry_sdram_slv_axi4_ib_int_async,
  
// Instance: u_ib_sys_gp_apb4_ib_s, Port: sys_gp_apb4_ib_m_async

  a_data_sys_gp_apb4_ib_int_async,
  a_rpntr_gry_sys_gp_apb4_ib_int_async,
  a_rpntr_bin_sys_gp_apb4_ib_int_async,
  a_wpntr_gry_sys_gp_apb4_ib_int_async,
  d_data_sys_gp_apb4_ib_int_async,
  d_rpntr_gry_sys_gp_apb4_ib_int_async,
  d_rpntr_bin_sys_gp_apb4_ib_int_async,
  d_wpntr_gry_sys_gp_apb4_ib_int_async,
  w_data_sys_gp_apb4_ib_int_async,
  w_rpntr_gry_sys_gp_apb4_ib_int_async,
  w_rpntr_bin_sys_gp_apb4_ib_int_async,
  w_wpntr_gry_sys_gp_apb4_ib_int_async,
  
// Instance: u_ib_tpv_gp_apb4_ib_s, Port: tpv_gp_apb4_ib_m_async

  a_data_tpv_gp_apb4_ib_int_async,
  a_rpntr_gry_tpv_gp_apb4_ib_int_async,
  a_rpntr_bin_tpv_gp_apb4_ib_int_async,
  a_wpntr_gry_tpv_gp_apb4_ib_int_async,
  d_data_tpv_gp_apb4_ib_int_async,
  d_rpntr_gry_tpv_gp_apb4_ib_int_async,
  d_rpntr_bin_tpv_gp_apb4_ib_int_async,
  d_wpntr_gry_tpv_gp_apb4_ib_int_async,
  w_data_tpv_gp_apb4_ib_int_async,
  w_rpntr_gry_tpv_gp_apb4_ib_int_async,
  w_rpntr_bin_tpv_gp_apb4_ib_int_async,
  w_wpntr_gry_tpv_gp_apb4_ib_int_async,
  
// Instance: u_ib_vgalcd_mst_axi4_ib_m, Port: vgalcd_mst_axi4_ib_s_async

  aw_data_vgalcd_mst_axi4_ib_int_async,
  aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  b_data_vgalcd_mst_axi4_ib_int_async,
  b_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  b_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  b_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  ar_data_vgalcd_mst_axi4_ib_int_async,
  ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  r_data_vgalcd_mst_axi4_ib_int_async,
  r_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  r_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  r_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  w_data_vgalcd_mst_axi4_ib_int_async,
  w_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  w_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  w_wpntr_gry_vgalcd_mst_axi4_ib_int_async,

//  Non-bus signals

  clk_core_200_800mclk,
  clk_core_200_800mresetn

);



//-----------------------------------------------------------------------------
// Port Declarations
//-----------------------------------------------------------------------------


// Instance: u_amib_dma_axi4_cpu, Port: dma_axi4_cpu_m

output [3:0]  awid_dma_axi4_cpu_m;
output [31:0] awaddr_dma_axi4_cpu_m;
output [7:0]  awlen_dma_axi4_cpu_m;
output [2:0]  awsize_dma_axi4_cpu_m;
output [1:0]  awburst_dma_axi4_cpu_m;
output        awlock_dma_axi4_cpu_m;
output [3:0]  awcache_dma_axi4_cpu_m;
output [2:0]  awprot_dma_axi4_cpu_m;
output        awvalid_dma_axi4_cpu_m;
input         awready_dma_axi4_cpu_m;
output [31:0] wdata_dma_axi4_cpu_m;
output [3:0]  wstrb_dma_axi4_cpu_m;
output        wlast_dma_axi4_cpu_m;
output        wvalid_dma_axi4_cpu_m;
input         wready_dma_axi4_cpu_m;
input  [3:0]  bid_dma_axi4_cpu_m;
input  [1:0]  bresp_dma_axi4_cpu_m;
input         bvalid_dma_axi4_cpu_m;
output        bready_dma_axi4_cpu_m;
output [3:0]  arid_dma_axi4_cpu_m;
output [31:0] araddr_dma_axi4_cpu_m;
output [7:0]  arlen_dma_axi4_cpu_m;
output [2:0]  arsize_dma_axi4_cpu_m;
output [1:0]  arburst_dma_axi4_cpu_m;
output        arlock_dma_axi4_cpu_m;
output [3:0]  arcache_dma_axi4_cpu_m;
output [2:0]  arprot_dma_axi4_cpu_m;
output        arvalid_dma_axi4_cpu_m;
input         arready_dma_axi4_cpu_m;
input  [3:0]  rid_dma_axi4_cpu_m;
input  [31:0] rdata_dma_axi4_cpu_m;
input  [1:0]  rresp_dma_axi4_cpu_m;
input         rlast_dma_axi4_cpu_m;
input         rvalid_dma_axi4_cpu_m;
output        rready_dma_axi4_cpu_m;

// Instance: u_amib_sram_slv_axi4, Port: sram_slv_axi4_m

output [3:0]  awid_sram_slv_axi4;
output [31:0] awaddr_sram_slv_axi4;
output [7:0]  awlen_sram_slv_axi4;
output [2:0]  awsize_sram_slv_axi4;
output [1:0]  awburst_sram_slv_axi4;
output        awlock_sram_slv_axi4;
output [3:0]  awcache_sram_slv_axi4;
output [2:0]  awprot_sram_slv_axi4;
output        awvalid_sram_slv_axi4;
input         awready_sram_slv_axi4;
output [63:0] wdata_sram_slv_axi4;
output [7:0]  wstrb_sram_slv_axi4;
output        wlast_sram_slv_axi4;
output        wvalid_sram_slv_axi4;
input         wready_sram_slv_axi4;
input  [3:0]  bid_sram_slv_axi4;
input  [1:0]  bresp_sram_slv_axi4;
input         bvalid_sram_slv_axi4;
output        bready_sram_slv_axi4;
output [3:0]  arid_sram_slv_axi4;
output [31:0] araddr_sram_slv_axi4;
output [7:0]  arlen_sram_slv_axi4;
output [2:0]  arsize_sram_slv_axi4;
output [1:0]  arburst_sram_slv_axi4;
output        arlock_sram_slv_axi4;
output [3:0]  arcache_sram_slv_axi4;
output [2:0]  arprot_sram_slv_axi4;
output        arvalid_sram_slv_axi4;
input         arready_sram_slv_axi4;
input  [3:0]  rid_sram_slv_axi4;
input  [63:0] rdata_sram_slv_axi4;
input  [1:0]  rresp_sram_slv_axi4;
input         rlast_sram_slv_axi4;
input         rvalid_sram_slv_axi4;
output        rready_sram_slv_axi4;

// Instance: u_asib_cpu_mst_axi4, Port: cpu_mst_axi4_s

input  [2:0]  awid_cpu_mst_axi4;
input  [31:0] awaddr_cpu_mst_axi4;
input  [7:0]  awlen_cpu_mst_axi4;
input  [2:0]  awsize_cpu_mst_axi4;
input  [1:0]  awburst_cpu_mst_axi4;
input         awlock_cpu_mst_axi4;
input  [3:0]  awcache_cpu_mst_axi4;
input  [2:0]  awprot_cpu_mst_axi4;
input         awvalid_cpu_mst_axi4;
output        awready_cpu_mst_axi4;
input  [31:0] wdata_cpu_mst_axi4;
input  [3:0]  wstrb_cpu_mst_axi4;
input         wlast_cpu_mst_axi4;
input         wvalid_cpu_mst_axi4;
output        wready_cpu_mst_axi4;
output [2:0]  bid_cpu_mst_axi4;
output [1:0]  bresp_cpu_mst_axi4;
output        bvalid_cpu_mst_axi4;
input         bready_cpu_mst_axi4;
input  [2:0]  arid_cpu_mst_axi4;
input  [31:0] araddr_cpu_mst_axi4;
input  [7:0]  arlen_cpu_mst_axi4;
input  [2:0]  arsize_cpu_mst_axi4;
input  [1:0]  arburst_cpu_mst_axi4;
input         arlock_cpu_mst_axi4;
input  [3:0]  arcache_cpu_mst_axi4;
input  [2:0]  arprot_cpu_mst_axi4;
input         arvalid_cpu_mst_axi4;
output        arready_cpu_mst_axi4;
output [2:0]  rid_cpu_mst_axi4;
output [31:0] rdata_cpu_mst_axi4;
output [1:0]  rresp_cpu_mst_axi4;
output        rlast_cpu_mst_axi4;
output        rvalid_cpu_mst_axi4;
input         rready_cpu_mst_axi4;

// Instance: u_ib_chiplink_slv_axi4_tpv_ib_s, Port: chiplink_slv_axi4_tpv_ib_m_async

output [60:0] aw_data_chiplink_slv_axi4_tpv_ib_int_async;
input  [1:0]  aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
input         aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
output [1:0]  aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
input  [5:0]  b_data_chiplink_slv_axi4_tpv_ib_int_async;
output [1:0]  b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
output        b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
input  [1:0]  b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
output [60:0] ar_data_chiplink_slv_axi4_tpv_ib_int_async;
input  [1:0]  ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
input         ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
output [1:0]  ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
input  [70:0] r_data_chiplink_slv_axi4_tpv_ib_int_async;
output [1:0]  r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
output        r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
input  [1:0]  r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
output [72:0] w_data_chiplink_slv_axi4_tpv_ib_int_async;
input  [1:0]  w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
input         w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
output [1:0]  w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;

// Instance: u_ib_dma_axi4_cpu_ib_m, Port: dma_axi4_cpu_ib_s_async

input  [57:0] aw_data_dma_axi4_cpu_ib_int_async;
output [1:0]  aw_rpntr_gry_dma_axi4_cpu_ib_int_async;
output        aw_rpntr_bin_dma_axi4_cpu_ib_int_async;
input  [1:0]  aw_wpntr_gry_dma_axi4_cpu_ib_int_async;
output [5:0]  b_data_dma_axi4_cpu_ib_int_async;
input  [1:0]  b_rpntr_gry_dma_axi4_cpu_ib_int_async;
input         b_rpntr_bin_dma_axi4_cpu_ib_int_async;
output [1:0]  b_wpntr_gry_dma_axi4_cpu_ib_int_async;
input  [68:0] ar_data_dma_axi4_cpu_ib_int_async;
output [1:0]  ar_rpntr_gry_dma_axi4_cpu_ib_int_async;
output        ar_rpntr_bin_dma_axi4_cpu_ib_int_async;
input  [1:0]  ar_wpntr_gry_dma_axi4_cpu_ib_int_async;
output [72:0] r_data_dma_axi4_cpu_ib_int_async;
input  [1:0]  r_rpntr_gry_dma_axi4_cpu_ib_int_async;
input         r_rpntr_bin_dma_axi4_cpu_ib_int_async;
output [1:0]  r_wpntr_gry_dma_axi4_cpu_ib_int_async;
input  [72:0] w_data_dma_axi4_cpu_ib_int_async;
output [1:0]  w_rpntr_gry_dma_axi4_cpu_ib_int_async;
output        w_rpntr_bin_dma_axi4_cpu_ib_int_async;
input  [1:0]  w_wpntr_gry_dma_axi4_cpu_ib_int_async;

// Instance: u_ib_perip0_gp_apb4_ib_s, Port: perip0_gp_apb4_ib_m_async

output [61:0] a_data_perip0_gp_apb4_ib_int_async;
input  [1:0]  a_rpntr_gry_perip0_gp_apb4_ib_int_async;
input         a_rpntr_bin_perip0_gp_apb4_ib_int_async;
output [1:0]  a_wpntr_gry_perip0_gp_apb4_ib_int_async;
input  [39:0] d_data_perip0_gp_apb4_ib_int_async;
output [1:0]  d_rpntr_gry_perip0_gp_apb4_ib_int_async;
output        d_rpntr_bin_perip0_gp_apb4_ib_int_async;
input  [1:0]  d_wpntr_gry_perip0_gp_apb4_ib_int_async;
output [36:0] w_data_perip0_gp_apb4_ib_int_async;
input  [1:0]  w_rpntr_gry_perip0_gp_apb4_ib_int_async;
input         w_rpntr_bin_perip0_gp_apb4_ib_int_async;
output [1:0]  w_wpntr_gry_perip0_gp_apb4_ib_int_async;

// Instance: u_ib_perip1_gp_apb4_ib_s, Port: perip1_gp_apb4_ib_m_async

output [61:0] a_data_perip1_gp_apb4_ib_int_async;
input  [1:0]  a_rpntr_gry_perip1_gp_apb4_ib_int_async;
input         a_rpntr_bin_perip1_gp_apb4_ib_int_async;
output [1:0]  a_wpntr_gry_perip1_gp_apb4_ib_int_async;
input  [39:0] d_data_perip1_gp_apb4_ib_int_async;
output [1:0]  d_rpntr_gry_perip1_gp_apb4_ib_int_async;
output        d_rpntr_bin_perip1_gp_apb4_ib_int_async;
input  [1:0]  d_wpntr_gry_perip1_gp_apb4_ib_int_async;
output [36:0] w_data_perip1_gp_apb4_ib_int_async;
input  [1:0]  w_rpntr_gry_perip1_gp_apb4_ib_int_async;
input         w_rpntr_bin_perip1_gp_apb4_ib_int_async;
output [1:0]  w_wpntr_gry_perip1_gp_apb4_ib_int_async;

// Instance: u_ib_psram_slv_axi4_ib_s, Port: psram_slv_axi4_ib_m_async

output [60:0] aw_data_psram_slv_axi4_ib_int_async;
input  [1:0]  aw_rpntr_gry_psram_slv_axi4_ib_int_async;
input         aw_rpntr_bin_psram_slv_axi4_ib_int_async;
output [1:0]  aw_wpntr_gry_psram_slv_axi4_ib_int_async;
input  [5:0]  b_data_psram_slv_axi4_ib_int_async;
output [1:0]  b_rpntr_gry_psram_slv_axi4_ib_int_async;
output        b_rpntr_bin_psram_slv_axi4_ib_int_async;
input  [1:0]  b_wpntr_gry_psram_slv_axi4_ib_int_async;
output [60:0] ar_data_psram_slv_axi4_ib_int_async;
input  [1:0]  ar_rpntr_gry_psram_slv_axi4_ib_int_async;
input         ar_rpntr_bin_psram_slv_axi4_ib_int_async;
output [1:0]  ar_wpntr_gry_psram_slv_axi4_ib_int_async;
input  [70:0] r_data_psram_slv_axi4_ib_int_async;
output [1:0]  r_rpntr_gry_psram_slv_axi4_ib_int_async;
output        r_rpntr_bin_psram_slv_axi4_ib_int_async;
input  [1:0]  r_wpntr_gry_psram_slv_axi4_ib_int_async;
output [72:0] w_data_psram_slv_axi4_ib_int_async;
input  [1:0]  w_rpntr_gry_psram_slv_axi4_ib_int_async;
input         w_rpntr_bin_psram_slv_axi4_ib_int_async;
output [1:0]  w_wpntr_gry_psram_slv_axi4_ib_int_async;

// Instance: u_ib_sdram_slv_axi4_ib_s, Port: sdram_slv_axi4_ib_m_async

output [60:0] aw_data_sdram_slv_axi4_ib_int_async;
input  [1:0]  aw_rpntr_gry_sdram_slv_axi4_ib_int_async;
input         aw_rpntr_bin_sdram_slv_axi4_ib_int_async;
output [1:0]  aw_wpntr_gry_sdram_slv_axi4_ib_int_async;
input  [5:0]  b_data_sdram_slv_axi4_ib_int_async;
output [1:0]  b_rpntr_gry_sdram_slv_axi4_ib_int_async;
output        b_rpntr_bin_sdram_slv_axi4_ib_int_async;
input  [1:0]  b_wpntr_gry_sdram_slv_axi4_ib_int_async;
output [60:0] ar_data_sdram_slv_axi4_ib_int_async;
input  [1:0]  ar_rpntr_gry_sdram_slv_axi4_ib_int_async;
input         ar_rpntr_bin_sdram_slv_axi4_ib_int_async;
output [1:0]  ar_wpntr_gry_sdram_slv_axi4_ib_int_async;
input  [38:0] r_data_sdram_slv_axi4_ib_int_async;
output [1:0]  r_rpntr_gry_sdram_slv_axi4_ib_int_async;
output        r_rpntr_bin_sdram_slv_axi4_ib_int_async;
input  [1:0]  r_wpntr_gry_sdram_slv_axi4_ib_int_async;
output [36:0] w_data_sdram_slv_axi4_ib_int_async;
input  [1:0]  w_rpntr_gry_sdram_slv_axi4_ib_int_async;
input         w_rpntr_bin_sdram_slv_axi4_ib_int_async;
output [1:0]  w_wpntr_gry_sdram_slv_axi4_ib_int_async;

// Instance: u_ib_sys_gp_apb4_ib_s, Port: sys_gp_apb4_ib_m_async

output [61:0] a_data_sys_gp_apb4_ib_int_async;
input  [1:0]  a_rpntr_gry_sys_gp_apb4_ib_int_async;
input         a_rpntr_bin_sys_gp_apb4_ib_int_async;
output [1:0]  a_wpntr_gry_sys_gp_apb4_ib_int_async;
input  [39:0] d_data_sys_gp_apb4_ib_int_async;
output [1:0]  d_rpntr_gry_sys_gp_apb4_ib_int_async;
output        d_rpntr_bin_sys_gp_apb4_ib_int_async;
input  [1:0]  d_wpntr_gry_sys_gp_apb4_ib_int_async;
output [36:0] w_data_sys_gp_apb4_ib_int_async;
input  [1:0]  w_rpntr_gry_sys_gp_apb4_ib_int_async;
input         w_rpntr_bin_sys_gp_apb4_ib_int_async;
output [1:0]  w_wpntr_gry_sys_gp_apb4_ib_int_async;

// Instance: u_ib_tpv_gp_apb4_ib_s, Port: tpv_gp_apb4_ib_m_async

output [61:0] a_data_tpv_gp_apb4_ib_int_async;
input  [1:0]  a_rpntr_gry_tpv_gp_apb4_ib_int_async;
input         a_rpntr_bin_tpv_gp_apb4_ib_int_async;
output [1:0]  a_wpntr_gry_tpv_gp_apb4_ib_int_async;
input  [39:0] d_data_tpv_gp_apb4_ib_int_async;
output [1:0]  d_rpntr_gry_tpv_gp_apb4_ib_int_async;
output        d_rpntr_bin_tpv_gp_apb4_ib_int_async;
input  [1:0]  d_wpntr_gry_tpv_gp_apb4_ib_int_async;
output [36:0] w_data_tpv_gp_apb4_ib_int_async;
input  [1:0]  w_rpntr_gry_tpv_gp_apb4_ib_int_async;
input         w_rpntr_bin_tpv_gp_apb4_ib_int_async;
output [1:0]  w_wpntr_gry_tpv_gp_apb4_ib_int_async;

// Instance: u_ib_vgalcd_mst_axi4_ib_m, Port: vgalcd_mst_axi4_ib_s_async

input  [64:0] aw_data_vgalcd_mst_axi4_ib_int_async;
output [1:0]  aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
output        aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
output [4:0]  b_data_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  b_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
input         b_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
output [1:0]  b_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
input  [75:0] ar_data_vgalcd_mst_axi4_ib_int_async;
output [1:0]  ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
output        ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
output [71:0] r_data_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  r_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
input         r_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
output [1:0]  r_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
input  [72:0] w_data_vgalcd_mst_axi4_ib_int_async;
output [1:0]  w_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
output        w_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  w_wpntr_gry_vgalcd_mst_axi4_ib_int_async;

//  Non-bus signals

input         clk_core_200_800mclk;
input         clk_core_200_800mresetn;



//-----------------------------------------------------------------------------
// Internal Wire Declarations
//-----------------------------------------------------------------------------

wire   [61:0]  a_data_perip0_gp_apb4_ib_int_async;
wire   [61:0]  a_data_perip1_gp_apb4_ib_int_async;
wire   [61:0]  a_data_sys_gp_apb4_ib_int_async;
wire   [61:0]  a_data_tpv_gp_apb4_ib_int_async;
wire   [1:0]   a_wpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   a_wpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   a_wpntr_gry_sys_gp_apb4_ib_int_async;
wire   [1:0]   a_wpntr_gry_tpv_gp_apb4_ib_int_async;
wire   [60:0]  ar_data_chiplink_slv_axi4_tpv_ib_int_async;
wire   [60:0]  ar_data_psram_slv_axi4_ib_int_async;
wire   [60:0]  ar_data_sdram_slv_axi4_ib_int_async;
wire           ar_rpntr_bin_dma_axi4_cpu_ib_int_async;
wire           ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   ar_rpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   ar_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   ar_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [31:0]  araddr_dma_axi4_cpu_m;
wire   [31:0]  araddr_sram_slv_axi4;
wire   [1:0]   arburst_dma_axi4_cpu_m;
wire   [1:0]   arburst_sram_slv_axi4;
wire   [3:0]   arcache_dma_axi4_cpu_m;
wire   [3:0]   arcache_sram_slv_axi4;
wire   [3:0]   arid_dma_axi4_cpu_m;
wire   [3:0]   arid_sram_slv_axi4;
wire   [7:0]   arlen_dma_axi4_cpu_m;
wire   [7:0]   arlen_sram_slv_axi4;
wire           arlock_dma_axi4_cpu_m;
wire           arlock_sram_slv_axi4;
wire   [2:0]   arprot_dma_axi4_cpu_m;
wire   [2:0]   arprot_sram_slv_axi4;
wire           arready_cpu_mst_axi4;
wire   [2:0]   arsize_dma_axi4_cpu_m;
wire   [2:0]   arsize_sram_slv_axi4;
wire           arvalid_dma_axi4_cpu_m;
wire           arvalid_sram_slv_axi4;
wire   [60:0]  aw_data_chiplink_slv_axi4_tpv_ib_int_async;
wire   [60:0]  aw_data_psram_slv_axi4_ib_int_async;
wire   [60:0]  aw_data_sdram_slv_axi4_ib_int_async;
wire           aw_rpntr_bin_dma_axi4_cpu_ib_int_async;
wire           aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   aw_rpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   aw_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   aw_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [31:0]  awaddr_dma_axi4_cpu_m;
wire   [31:0]  awaddr_sram_slv_axi4;
wire   [1:0]   awburst_dma_axi4_cpu_m;
wire   [1:0]   awburst_sram_slv_axi4;
wire   [3:0]   awcache_dma_axi4_cpu_m;
wire   [3:0]   awcache_sram_slv_axi4;
wire   [3:0]   awid_dma_axi4_cpu_m;
wire   [3:0]   awid_sram_slv_axi4;
wire   [7:0]   awlen_dma_axi4_cpu_m;
wire   [7:0]   awlen_sram_slv_axi4;
wire           awlock_dma_axi4_cpu_m;
wire           awlock_sram_slv_axi4;
wire   [2:0]   awprot_dma_axi4_cpu_m;
wire   [2:0]   awprot_sram_slv_axi4;
wire           awready_cpu_mst_axi4;
wire   [2:0]   awsize_dma_axi4_cpu_m;
wire   [2:0]   awsize_sram_slv_axi4;
wire           awvalid_dma_axi4_cpu_m;
wire           awvalid_sram_slv_axi4;
wire   [5:0]   b_data_dma_axi4_cpu_ib_int_async;
wire   [4:0]   b_data_vgalcd_mst_axi4_ib_int_async;
wire           b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
wire           b_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           b_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   b_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   b_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   b_wpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   b_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [2:0]   bid_cpu_mst_axi4;
wire           bready_dma_axi4_cpu_m;
wire           bready_sram_slv_axi4;
wire   [1:0]   bresp_cpu_mst_axi4;
wire           bvalid_cpu_mst_axi4;
wire           d_rpntr_bin_perip0_gp_apb4_ib_int_async;
wire           d_rpntr_bin_perip1_gp_apb4_ib_int_async;
wire           d_rpntr_bin_sys_gp_apb4_ib_int_async;
wire           d_rpntr_bin_tpv_gp_apb4_ib_int_async;
wire   [1:0]   d_rpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   d_rpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   d_rpntr_gry_sys_gp_apb4_ib_int_async;
wire   [1:0]   d_rpntr_gry_tpv_gp_apb4_ib_int_async;
wire   [72:0]  r_data_dma_axi4_cpu_ib_int_async;
wire   [71:0]  r_data_vgalcd_mst_axi4_ib_int_async;
wire           r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
wire           r_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           r_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   r_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   r_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   r_wpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   r_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [31:0]  rdata_cpu_mst_axi4;
wire   [2:0]   rid_cpu_mst_axi4;
wire           rlast_cpu_mst_axi4;
wire           rready_dma_axi4_cpu_m;
wire           rready_sram_slv_axi4;
wire   [1:0]   rresp_cpu_mst_axi4;
wire           rvalid_cpu_mst_axi4;
wire   [72:0]  w_data_chiplink_slv_axi4_tpv_ib_int_async;
wire   [36:0]  w_data_perip0_gp_apb4_ib_int_async;
wire   [36:0]  w_data_perip1_gp_apb4_ib_int_async;
wire   [72:0]  w_data_psram_slv_axi4_ib_int_async;
wire   [36:0]  w_data_sdram_slv_axi4_ib_int_async;
wire   [36:0]  w_data_sys_gp_apb4_ib_int_async;
wire   [36:0]  w_data_tpv_gp_apb4_ib_int_async;
wire           w_rpntr_bin_dma_axi4_cpu_ib_int_async;
wire           w_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   w_rpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   w_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   w_wpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   w_wpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   w_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   w_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   w_wpntr_gry_sys_gp_apb4_ib_int_async;
wire   [1:0]   w_wpntr_gry_tpv_gp_apb4_ib_int_async;
wire   [31:0]  wdata_dma_axi4_cpu_m;
wire   [63:0]  wdata_sram_slv_axi4;
wire           wlast_dma_axi4_cpu_m;
wire           wlast_sram_slv_axi4;
wire           wready_cpu_mst_axi4;
wire   [3:0]   wstrb_dma_axi4_cpu_m;
wire   [7:0]   wstrb_sram_slv_axi4;
wire           wvalid_dma_axi4_cpu_m;
wire           wvalid_sram_slv_axi4;
wire           arready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           awready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [3:0]   bid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [1:0]   bresp_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           bvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [31:0]  rdata_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [3:0]   rid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           rlast_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [1:0]   rresp_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           rvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           wready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           arready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           awready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [3:0]   bid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [1:0]   bresp_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           bvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [63:0]  rdata_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [3:0]   rid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           rlast_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [1:0]   rresp_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           rvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           wready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [31:0]  araddr_cpu_mst_axi4_switch2_axi_s_0;
wire   [1:0]   arburst_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   arcache_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   arid_cpu_mst_axi4_switch2_axi_s_0;
wire   [7:0]   arlen_cpu_mst_axi4_switch2_axi_s_0;
wire           arlock_cpu_mst_axi4_switch2_axi_s_0;
wire   [2:0]   arprot_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   arqv_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   arregion_cpu_mst_axi4_switch2_axi_s_0;
wire   [2:0]   arsize_cpu_mst_axi4_switch2_axi_s_0;
wire           arvalid_cpu_mst_axi4_switch2_axi_s_0;
wire   [8:0]   arvalid_vect_cpu_mst_axi4_switch2_axi_s_0;
wire   [31:0]  awaddr_cpu_mst_axi4_switch2_axi_s_0;
wire   [1:0]   awburst_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   awcache_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   awid_cpu_mst_axi4_switch2_axi_s_0;
wire   [7:0]   awlen_cpu_mst_axi4_switch2_axi_s_0;
wire           awlock_cpu_mst_axi4_switch2_axi_s_0;
wire   [2:0]   awprot_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   awqv_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   awregion_cpu_mst_axi4_switch2_axi_s_0;
wire   [2:0]   awsize_cpu_mst_axi4_switch2_axi_s_0;
wire           awvalid_cpu_mst_axi4_switch2_axi_s_0;
wire   [8:0]   awvalid_vect_cpu_mst_axi4_switch2_axi_s_0;
wire           bready_cpu_mst_axi4_switch2_axi_s_0;
wire           rready_cpu_mst_axi4_switch2_axi_s_0;
wire   [31:0]  wdata_cpu_mst_axi4_switch2_axi_s_0;
wire           wlast_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   wstrb_cpu_mst_axi4_switch2_axi_s_0;
wire           wvalid_cpu_mst_axi4_switch2_axi_s_0;
wire   [31:0]  araddr_switch2_sram_slv_axi4_ib_axi4_s;
wire   [31:0]  araddr_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [31:0]  araddr_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [31:0]  araddr_switch2_psram_slv_axi4_ib_axi4_s;
wire   [31:0]  araddr_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [31:0]  araddr_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [31:0]  araddr_switch2_sys_gp_apb4_ib_axi4_s;
wire   [31:0]  araddr_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [1:0]   arburst_switch2_sram_slv_axi4_ib_axi4_s;
wire   [1:0]   arburst_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [1:0]   arburst_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [1:0]   arburst_switch2_psram_slv_axi4_ib_axi4_s;
wire   [1:0]   arburst_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [1:0]   arburst_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [1:0]   arburst_switch2_sys_gp_apb4_ib_axi4_s;
wire   [1:0]   arburst_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [3:0]   arcache_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   arcache_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   arcache_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   arcache_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   arcache_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   arcache_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   arcache_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   arcache_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [3:0]   arid_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   arid_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   arid_switch2_ds_1_axi_s_0;
wire   [3:0]   arid_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   arid_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   arid_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   arid_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   arid_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   arid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [7:0]   arlen_switch2_sram_slv_axi4_ib_axi4_s;
wire   [7:0]   arlen_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [7:0]   arlen_switch2_ds_1_axi_s_0;
wire   [7:0]   arlen_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [7:0]   arlen_switch2_psram_slv_axi4_ib_axi4_s;
wire   [7:0]   arlen_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [7:0]   arlen_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [7:0]   arlen_switch2_sys_gp_apb4_ib_axi4_s;
wire   [7:0]   arlen_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           arlock_switch2_sram_slv_axi4_ib_axi4_s;
wire           arlock_switch2_perip0_gp_apb4_ib_axi4_s;
wire           arlock_switch2_perip1_gp_apb4_ib_axi4_s;
wire           arlock_switch2_psram_slv_axi4_ib_axi4_s;
wire           arlock_switch2_sdram_slv_axi4_ib_axi4_s;
wire           arlock_switch2_tpv_gp_apb4_ib_axi4_s;
wire           arlock_switch2_sys_gp_apb4_ib_axi4_s;
wire           arlock_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [2:0]   arprot_switch2_sram_slv_axi4_ib_axi4_s;
wire   [2:0]   arprot_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [2:0]   arprot_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [2:0]   arprot_switch2_psram_slv_axi4_ib_axi4_s;
wire   [2:0]   arprot_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [2:0]   arprot_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [2:0]   arprot_switch2_sys_gp_apb4_ib_axi4_s;
wire   [2:0]   arprot_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           arready_cpu_mst_axi4_switch2_axi_s_0;
wire           arready_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   arregion_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   arregion_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   arregion_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   arregion_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   arregion_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   arregion_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   arregion_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   arregion_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [2:0]   arsize_switch2_sram_slv_axi4_ib_axi4_s;
wire   [2:0]   arsize_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [2:0]   arsize_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [2:0]   arsize_switch2_psram_slv_axi4_ib_axi4_s;
wire   [2:0]   arsize_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [2:0]   arsize_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [2:0]   arsize_switch2_sys_gp_apb4_ib_axi4_s;
wire   [2:0]   arsize_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           arvalid_switch2_sram_slv_axi4_ib_axi4_s;
wire           arvalid_switch2_perip0_gp_apb4_ib_axi4_s;
wire           arvalid_switch2_ds_1_axi_s_0;
wire           arvalid_switch2_perip1_gp_apb4_ib_axi4_s;
wire           arvalid_switch2_psram_slv_axi4_ib_axi4_s;
wire           arvalid_switch2_sdram_slv_axi4_ib_axi4_s;
wire           arvalid_switch2_tpv_gp_apb4_ib_axi4_s;
wire           arvalid_switch2_sys_gp_apb4_ib_axi4_s;
wire           arvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [31:0]  awaddr_switch2_sram_slv_axi4_ib_axi4_s;
wire   [31:0]  awaddr_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [31:0]  awaddr_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [31:0]  awaddr_switch2_psram_slv_axi4_ib_axi4_s;
wire   [31:0]  awaddr_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [31:0]  awaddr_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [31:0]  awaddr_switch2_sys_gp_apb4_ib_axi4_s;
wire   [31:0]  awaddr_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [1:0]   awburst_switch2_sram_slv_axi4_ib_axi4_s;
wire   [1:0]   awburst_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [1:0]   awburst_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [1:0]   awburst_switch2_psram_slv_axi4_ib_axi4_s;
wire   [1:0]   awburst_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [1:0]   awburst_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [1:0]   awburst_switch2_sys_gp_apb4_ib_axi4_s;
wire   [1:0]   awburst_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [3:0]   awcache_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   awcache_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   awcache_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   awcache_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   awcache_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   awcache_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   awcache_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   awcache_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [3:0]   awid_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   awid_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   awid_switch2_ds_1_axi_s_0;
wire   [3:0]   awid_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   awid_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   awid_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   awid_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   awid_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   awid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [7:0]   awlen_switch2_sram_slv_axi4_ib_axi4_s;
wire   [7:0]   awlen_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [7:0]   awlen_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [7:0]   awlen_switch2_psram_slv_axi4_ib_axi4_s;
wire   [7:0]   awlen_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [7:0]   awlen_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [7:0]   awlen_switch2_sys_gp_apb4_ib_axi4_s;
wire   [7:0]   awlen_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           awlock_switch2_sram_slv_axi4_ib_axi4_s;
wire           awlock_switch2_perip0_gp_apb4_ib_axi4_s;
wire           awlock_switch2_perip1_gp_apb4_ib_axi4_s;
wire           awlock_switch2_psram_slv_axi4_ib_axi4_s;
wire           awlock_switch2_sdram_slv_axi4_ib_axi4_s;
wire           awlock_switch2_tpv_gp_apb4_ib_axi4_s;
wire           awlock_switch2_sys_gp_apb4_ib_axi4_s;
wire           awlock_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [2:0]   awprot_switch2_sram_slv_axi4_ib_axi4_s;
wire   [2:0]   awprot_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [2:0]   awprot_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [2:0]   awprot_switch2_psram_slv_axi4_ib_axi4_s;
wire   [2:0]   awprot_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [2:0]   awprot_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [2:0]   awprot_switch2_sys_gp_apb4_ib_axi4_s;
wire   [2:0]   awprot_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           awready_cpu_mst_axi4_switch2_axi_s_0;
wire           awready_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   awregion_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   awregion_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   awregion_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   awregion_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   awregion_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   awregion_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   awregion_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   awregion_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [2:0]   awsize_switch2_sram_slv_axi4_ib_axi4_s;
wire   [2:0]   awsize_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [2:0]   awsize_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [2:0]   awsize_switch2_psram_slv_axi4_ib_axi4_s;
wire   [2:0]   awsize_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [2:0]   awsize_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [2:0]   awsize_switch2_sys_gp_apb4_ib_axi4_s;
wire   [2:0]   awsize_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           awvalid_switch2_sram_slv_axi4_ib_axi4_s;
wire           awvalid_switch2_perip0_gp_apb4_ib_axi4_s;
wire           awvalid_switch2_ds_1_axi_s_0;
wire           awvalid_switch2_perip1_gp_apb4_ib_axi4_s;
wire           awvalid_switch2_psram_slv_axi4_ib_axi4_s;
wire           awvalid_switch2_sdram_slv_axi4_ib_axi4_s;
wire           awvalid_switch2_tpv_gp_apb4_ib_axi4_s;
wire           awvalid_switch2_sys_gp_apb4_ib_axi4_s;
wire           awvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [3:0]   bid_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   bid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           bready_switch2_sram_slv_axi4_ib_axi4_s;
wire           bready_switch2_perip0_gp_apb4_ib_axi4_s;
wire           bready_switch2_ds_1_axi_s_0;
wire           bready_switch2_perip1_gp_apb4_ib_axi4_s;
wire           bready_switch2_psram_slv_axi4_ib_axi4_s;
wire           bready_switch2_sdram_slv_axi4_ib_axi4_s;
wire           bready_switch2_tpv_gp_apb4_ib_axi4_s;
wire           bready_switch2_sys_gp_apb4_ib_axi4_s;
wire           bready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [1:0]   bresp_cpu_mst_axi4_switch2_axi_s_0;
wire   [1:0]   bresp_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           bvalid_cpu_mst_axi4_switch2_axi_s_0;
wire           bvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [31:0]  rdata_cpu_mst_axi4_switch2_axi_s_0;
wire   [31:0]  rdata_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   rid_cpu_mst_axi4_switch2_axi_s_0;
wire   [3:0]   rid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           rlast_cpu_mst_axi4_switch2_axi_s_0;
wire           rlast_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           rready_switch2_sram_slv_axi4_ib_axi4_s;
wire           rready_switch2_perip0_gp_apb4_ib_axi4_s;
wire           rready_switch2_ds_1_axi_s_0;
wire           rready_switch2_perip1_gp_apb4_ib_axi4_s;
wire           rready_switch2_psram_slv_axi4_ib_axi4_s;
wire           rready_switch2_sdram_slv_axi4_ib_axi4_s;
wire           rready_switch2_tpv_gp_apb4_ib_axi4_s;
wire           rready_switch2_sys_gp_apb4_ib_axi4_s;
wire           rready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [1:0]   rresp_cpu_mst_axi4_switch2_axi_s_0;
wire   [1:0]   rresp_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           rvalid_cpu_mst_axi4_switch2_axi_s_0;
wire           rvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [31:0]  wdata_switch2_sram_slv_axi4_ib_axi4_s;
wire   [31:0]  wdata_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [31:0]  wdata_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [31:0]  wdata_switch2_psram_slv_axi4_ib_axi4_s;
wire   [31:0]  wdata_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [31:0]  wdata_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [31:0]  wdata_switch2_sys_gp_apb4_ib_axi4_s;
wire   [31:0]  wdata_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           wlast_switch2_sram_slv_axi4_ib_axi4_s;
wire           wlast_switch2_perip0_gp_apb4_ib_axi4_s;
wire           wlast_switch2_ds_1_axi_s_0;
wire           wlast_switch2_perip1_gp_apb4_ib_axi4_s;
wire           wlast_switch2_psram_slv_axi4_ib_axi4_s;
wire           wlast_switch2_sdram_slv_axi4_ib_axi4_s;
wire           wlast_switch2_tpv_gp_apb4_ib_axi4_s;
wire           wlast_switch2_sys_gp_apb4_ib_axi4_s;
wire           wlast_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           wready_cpu_mst_axi4_switch2_axi_s_0;
wire           wready_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   wstrb_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   wstrb_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   wstrb_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   wstrb_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   wstrb_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   wstrb_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   wstrb_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   wstrb_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           wvalid_switch2_sram_slv_axi4_ib_axi4_s;
wire           wvalid_switch2_perip0_gp_apb4_ib_axi4_s;
wire           wvalid_switch2_ds_1_axi_s_0;
wire           wvalid_switch2_perip1_gp_apb4_ib_axi4_s;
wire           wvalid_switch2_psram_slv_axi4_ib_axi4_s;
wire           wvalid_switch2_sdram_slv_axi4_ib_axi4_s;
wire           wvalid_switch2_tpv_gp_apb4_ib_axi4_s;
wire           wvalid_switch2_sys_gp_apb4_ib_axi4_s;
wire           wvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           arready_switch2_ds_1_axi_s_0;
wire           awready_switch2_ds_1_axi_s_0;
wire   [3:0]   bid_switch2_ds_1_axi_s_0;
wire   [1:0]   bresp_switch2_ds_1_axi_s_0;
wire           bvalid_switch2_ds_1_axi_s_0;
wire   [3:0]   rid_switch2_ds_1_axi_s_0;
wire           rlast_switch2_ds_1_axi_s_0;
wire   [1:0]   rresp_switch2_ds_1_axi_s_0;
wire           rvalid_switch2_ds_1_axi_s_0;
wire           wready_switch2_ds_1_axi_s_0;
wire           arready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           awready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [3:0]   bid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [1:0]   bresp_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           bvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [31:0]  rdata_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [3:0]   rid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           rlast_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [1:0]   rresp_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           rvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire           wready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s;
wire   [31:0]  araddr_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [1:0]   arburst_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [3:0]   arcache_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [3:0]   arid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [7:0]   arlen_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           arlock_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [2:0]   arprot_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [2:0]   arsize_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           arvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [31:0]  awaddr_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [1:0]   awburst_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [3:0]   awcache_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [3:0]   awid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [7:0]   awlen_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           awlock_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [2:0]   awprot_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [2:0]   awsize_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           awvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           bready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           rready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [31:0]  wdata_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           wlast_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire   [3:0]   wstrb_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           wvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s;
wire           arready_switch2_perip0_gp_apb4_ib_axi4_s;
wire           awready_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   bid_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [1:0]   bresp_switch2_perip0_gp_apb4_ib_axi4_s;
wire           bvalid_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [31:0]  rdata_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [3:0]   rid_switch2_perip0_gp_apb4_ib_axi4_s;
wire           rlast_switch2_perip0_gp_apb4_ib_axi4_s;
wire   [1:0]   rresp_switch2_perip0_gp_apb4_ib_axi4_s;
wire           rvalid_switch2_perip0_gp_apb4_ib_axi4_s;
wire           wready_switch2_perip0_gp_apb4_ib_axi4_s;
wire           arready_switch2_perip1_gp_apb4_ib_axi4_s;
wire           awready_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   bid_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [1:0]   bresp_switch2_perip1_gp_apb4_ib_axi4_s;
wire           bvalid_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [31:0]  rdata_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [3:0]   rid_switch2_perip1_gp_apb4_ib_axi4_s;
wire           rlast_switch2_perip1_gp_apb4_ib_axi4_s;
wire   [1:0]   rresp_switch2_perip1_gp_apb4_ib_axi4_s;
wire           rvalid_switch2_perip1_gp_apb4_ib_axi4_s;
wire           wready_switch2_perip1_gp_apb4_ib_axi4_s;
wire           arready_switch2_psram_slv_axi4_ib_axi4_s;
wire           awready_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   bid_switch2_psram_slv_axi4_ib_axi4_s;
wire   [1:0]   bresp_switch2_psram_slv_axi4_ib_axi4_s;
wire           bvalid_switch2_psram_slv_axi4_ib_axi4_s;
wire   [31:0]  rdata_switch2_psram_slv_axi4_ib_axi4_s;
wire   [3:0]   rid_switch2_psram_slv_axi4_ib_axi4_s;
wire           rlast_switch2_psram_slv_axi4_ib_axi4_s;
wire   [1:0]   rresp_switch2_psram_slv_axi4_ib_axi4_s;
wire           rvalid_switch2_psram_slv_axi4_ib_axi4_s;
wire           wready_switch2_psram_slv_axi4_ib_axi4_s;
wire           arready_switch2_sdram_slv_axi4_ib_axi4_s;
wire           awready_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   bid_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [1:0]   bresp_switch2_sdram_slv_axi4_ib_axi4_s;
wire           bvalid_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [31:0]  rdata_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [3:0]   rid_switch2_sdram_slv_axi4_ib_axi4_s;
wire           rlast_switch2_sdram_slv_axi4_ib_axi4_s;
wire   [1:0]   rresp_switch2_sdram_slv_axi4_ib_axi4_s;
wire           rvalid_switch2_sdram_slv_axi4_ib_axi4_s;
wire           wready_switch2_sdram_slv_axi4_ib_axi4_s;
wire           ar_ready_sram_slv_axi4_ib_int;
wire   [31:0]  araddr_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [1:0]   arburst_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [3:0]   arcache_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [3:0]   arid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [7:0]   arlen_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           arlock_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [2:0]   arprot_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [2:0]   arsize_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           arvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           aw_ready_sram_slv_axi4_ib_int;
wire   [31:0]  awaddr_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [1:0]   awburst_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [3:0]   awcache_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [3:0]   awid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [7:0]   awlen_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           awlock_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [2:0]   awprot_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [2:0]   awsize_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           awvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [5:0]   b_data_sram_slv_axi4_ib_int;
wire           b_valid_sram_slv_axi4_ib_int;
wire           bready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [70:0]  r_data_sram_slv_axi4_ib_int;
wire           r_valid_sram_slv_axi4_ib_int;
wire           rready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           w_ready_sram_slv_axi4_ib_int;
wire   [63:0]  wdata_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           wlast_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [7:0]   wstrb_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire           wvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s;
wire   [60:0]  ar_data_sram_slv_axi4_ib_int;
wire           ar_valid_sram_slv_axi4_ib_int;
wire           arready_switch2_sram_slv_axi4_ib_axi4_s;
wire   [60:0]  aw_data_sram_slv_axi4_ib_int;
wire           aw_valid_sram_slv_axi4_ib_int;
wire           awready_switch2_sram_slv_axi4_ib_axi4_s;
wire           b_ready_sram_slv_axi4_ib_int;
wire   [3:0]   bid_switch2_sram_slv_axi4_ib_axi4_s;
wire   [1:0]   bresp_switch2_sram_slv_axi4_ib_axi4_s;
wire           bvalid_switch2_sram_slv_axi4_ib_axi4_s;
wire           r_ready_sram_slv_axi4_ib_int;
wire   [31:0]  rdata_switch2_sram_slv_axi4_ib_axi4_s;
wire   [3:0]   rid_switch2_sram_slv_axi4_ib_axi4_s;
wire           rlast_switch2_sram_slv_axi4_ib_axi4_s;
wire   [1:0]   rresp_switch2_sram_slv_axi4_ib_axi4_s;
wire           rvalid_switch2_sram_slv_axi4_ib_axi4_s;
wire   [72:0]  w_data_sram_slv_axi4_ib_int;
wire           w_valid_sram_slv_axi4_ib_int;
wire           wready_switch2_sram_slv_axi4_ib_axi4_s;
wire           arready_switch2_sys_gp_apb4_ib_axi4_s;
wire           awready_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   bid_switch2_sys_gp_apb4_ib_axi4_s;
wire   [1:0]   bresp_switch2_sys_gp_apb4_ib_axi4_s;
wire           bvalid_switch2_sys_gp_apb4_ib_axi4_s;
wire   [31:0]  rdata_switch2_sys_gp_apb4_ib_axi4_s;
wire   [3:0]   rid_switch2_sys_gp_apb4_ib_axi4_s;
wire           rlast_switch2_sys_gp_apb4_ib_axi4_s;
wire   [1:0]   rresp_switch2_sys_gp_apb4_ib_axi4_s;
wire           rvalid_switch2_sys_gp_apb4_ib_axi4_s;
wire           wready_switch2_sys_gp_apb4_ib_axi4_s;
wire           arready_switch2_tpv_gp_apb4_ib_axi4_s;
wire           awready_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   bid_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [1:0]   bresp_switch2_tpv_gp_apb4_ib_axi4_s;
wire           bvalid_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [31:0]  rdata_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [3:0]   rid_switch2_tpv_gp_apb4_ib_axi4_s;
wire           rlast_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [1:0]   rresp_switch2_tpv_gp_apb4_ib_axi4_s;
wire           rvalid_switch2_tpv_gp_apb4_ib_axi4_s;
wire           wready_switch2_tpv_gp_apb4_ib_axi4_s;
wire   [31:0]  araddr_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [1:0]   arburst_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   arcache_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   arid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [7:0]   arlen_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           arlock_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [2:0]   arprot_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   arqv_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   arregion_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [2:0]   arsize_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           arvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   arvalid_vect_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [31:0]  awaddr_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [1:0]   awburst_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   awcache_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   awid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [7:0]   awlen_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           awlock_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [2:0]   awprot_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   awqv_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   awregion_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [2:0]   awsize_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           awvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   awvalid_vect_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           bready_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           rready_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [31:0]  wdata_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           wlast_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire   [3:0]   wstrb_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           wvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1;
wire           a_rpntr_bin_perip0_gp_apb4_ib_int_async;
wire           a_rpntr_bin_perip1_gp_apb4_ib_int_async;
wire           a_rpntr_bin_sys_gp_apb4_ib_int_async;
wire           a_rpntr_bin_tpv_gp_apb4_ib_int_async;
wire   [1:0]   a_rpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   a_rpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   a_rpntr_gry_sys_gp_apb4_ib_int_async;
wire   [1:0]   a_rpntr_gry_tpv_gp_apb4_ib_int_async;
wire   [68:0]  ar_data_dma_axi4_cpu_ib_int_async;
wire   [75:0]  ar_data_vgalcd_mst_axi4_ib_int_async;
wire           ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
wire           ar_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           ar_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   ar_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   ar_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   ar_wpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [31:0]  araddr_cpu_mst_axi4;
wire   [1:0]   arburst_cpu_mst_axi4;
wire   [3:0]   arcache_cpu_mst_axi4;
wire   [2:0]   arid_cpu_mst_axi4;
wire   [7:0]   arlen_cpu_mst_axi4;
wire           arlock_cpu_mst_axi4;
wire   [2:0]   arprot_cpu_mst_axi4;
wire           arready_dma_axi4_cpu_m;
wire           arready_sram_slv_axi4;
wire   [2:0]   arsize_cpu_mst_axi4;
wire           arvalid_cpu_mst_axi4;
wire   [57:0]  aw_data_dma_axi4_cpu_ib_int_async;
wire   [64:0]  aw_data_vgalcd_mst_axi4_ib_int_async;
wire           aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
wire           aw_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           aw_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   aw_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   aw_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   aw_wpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [31:0]  awaddr_cpu_mst_axi4;
wire   [1:0]   awburst_cpu_mst_axi4;
wire   [3:0]   awcache_cpu_mst_axi4;
wire   [2:0]   awid_cpu_mst_axi4;
wire   [7:0]   awlen_cpu_mst_axi4;
wire           awlock_cpu_mst_axi4;
wire   [2:0]   awprot_cpu_mst_axi4;
wire           awready_dma_axi4_cpu_m;
wire           awready_sram_slv_axi4;
wire   [2:0]   awsize_cpu_mst_axi4;
wire           awvalid_cpu_mst_axi4;
wire   [5:0]   b_data_chiplink_slv_axi4_tpv_ib_int_async;
wire   [5:0]   b_data_psram_slv_axi4_ib_int_async;
wire   [5:0]   b_data_sdram_slv_axi4_ib_int_async;
wire           b_rpntr_bin_dma_axi4_cpu_ib_int_async;
wire           b_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   b_rpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   b_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   b_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   b_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [3:0]   bid_dma_axi4_cpu_m;
wire   [3:0]   bid_sram_slv_axi4;
wire           bready_cpu_mst_axi4;
wire   [1:0]   bresp_dma_axi4_cpu_m;
wire   [1:0]   bresp_sram_slv_axi4;
wire           bvalid_dma_axi4_cpu_m;
wire           bvalid_sram_slv_axi4;
wire           clk_core_200_800mclk;
wire           clk_core_200_800mresetn;
wire   [39:0]  d_data_perip0_gp_apb4_ib_int_async;
wire   [39:0]  d_data_perip1_gp_apb4_ib_int_async;
wire   [39:0]  d_data_sys_gp_apb4_ib_int_async;
wire   [39:0]  d_data_tpv_gp_apb4_ib_int_async;
wire   [1:0]   d_wpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   d_wpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   d_wpntr_gry_sys_gp_apb4_ib_int_async;
wire   [1:0]   d_wpntr_gry_tpv_gp_apb4_ib_int_async;
wire   [70:0]  r_data_chiplink_slv_axi4_tpv_ib_int_async;
wire   [70:0]  r_data_psram_slv_axi4_ib_int_async;
wire   [38:0]  r_data_sdram_slv_axi4_ib_int_async;
wire           r_rpntr_bin_dma_axi4_cpu_ib_int_async;
wire           r_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   r_rpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   r_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   r_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   r_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [31:0]  rdata_dma_axi4_cpu_m;
wire   [63:0]  rdata_sram_slv_axi4;
wire   [3:0]   rid_dma_axi4_cpu_m;
wire   [3:0]   rid_sram_slv_axi4;
wire           rlast_dma_axi4_cpu_m;
wire           rlast_sram_slv_axi4;
wire           rready_cpu_mst_axi4;
wire   [1:0]   rresp_dma_axi4_cpu_m;
wire   [1:0]   rresp_sram_slv_axi4;
wire           rvalid_dma_axi4_cpu_m;
wire           rvalid_sram_slv_axi4;
wire   [72:0]  w_data_dma_axi4_cpu_ib_int_async;
wire   [72:0]  w_data_vgalcd_mst_axi4_ib_int_async;
wire           w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;
wire           w_rpntr_bin_perip0_gp_apb4_ib_int_async;
wire           w_rpntr_bin_perip1_gp_apb4_ib_int_async;
wire           w_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           w_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire           w_rpntr_bin_sys_gp_apb4_ib_int_async;
wire           w_rpntr_bin_tpv_gp_apb4_ib_int_async;
wire   [1:0]   w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;
wire   [1:0]   w_rpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   w_rpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   w_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   w_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   w_rpntr_gry_sys_gp_apb4_ib_int_async;
wire   [1:0]   w_rpntr_gry_tpv_gp_apb4_ib_int_async;
wire   [1:0]   w_wpntr_gry_dma_axi4_cpu_ib_int_async;
wire   [1:0]   w_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [31:0]  wdata_cpu_mst_axi4;
wire           wlast_cpu_mst_axi4;
wire           wready_dma_axi4_cpu_m;
wire           wready_sram_slv_axi4;
wire   [3:0]   wstrb_cpu_mst_axi4;
wire           wvalid_cpu_mst_axi4;



//-----------------------------------------------------------------------------
// Sub-Modules Instantiation
//-----------------------------------------------------------------------------

nic400_amib_dma_axi4_cpu_ysyx_rv32     u_amib_dma_axi4_cpu (
  .awid_dma_axi4_cpu_m  (awid_dma_axi4_cpu_m),
  .awaddr_dma_axi4_cpu_m (awaddr_dma_axi4_cpu_m),
  .awlen_dma_axi4_cpu_m (awlen_dma_axi4_cpu_m),
  .awsize_dma_axi4_cpu_m (awsize_dma_axi4_cpu_m),
  .awburst_dma_axi4_cpu_m (awburst_dma_axi4_cpu_m),
  .awlock_dma_axi4_cpu_m (awlock_dma_axi4_cpu_m),
  .awcache_dma_axi4_cpu_m (awcache_dma_axi4_cpu_m),
  .awprot_dma_axi4_cpu_m (awprot_dma_axi4_cpu_m),
  .awvalid_dma_axi4_cpu_m (awvalid_dma_axi4_cpu_m),
  .awready_dma_axi4_cpu_m (awready_dma_axi4_cpu_m),
  .wdata_dma_axi4_cpu_m (wdata_dma_axi4_cpu_m),
  .wstrb_dma_axi4_cpu_m (wstrb_dma_axi4_cpu_m),
  .wlast_dma_axi4_cpu_m (wlast_dma_axi4_cpu_m),
  .wvalid_dma_axi4_cpu_m (wvalid_dma_axi4_cpu_m),
  .wready_dma_axi4_cpu_m (wready_dma_axi4_cpu_m),
  .bid_dma_axi4_cpu_m   (bid_dma_axi4_cpu_m),
  .bresp_dma_axi4_cpu_m (bresp_dma_axi4_cpu_m),
  .bvalid_dma_axi4_cpu_m (bvalid_dma_axi4_cpu_m),
  .bready_dma_axi4_cpu_m (bready_dma_axi4_cpu_m),
  .arid_dma_axi4_cpu_m  (arid_dma_axi4_cpu_m),
  .araddr_dma_axi4_cpu_m (araddr_dma_axi4_cpu_m),
  .arlen_dma_axi4_cpu_m (arlen_dma_axi4_cpu_m),
  .arsize_dma_axi4_cpu_m (arsize_dma_axi4_cpu_m),
  .arburst_dma_axi4_cpu_m (arburst_dma_axi4_cpu_m),
  .arlock_dma_axi4_cpu_m (arlock_dma_axi4_cpu_m),
  .arcache_dma_axi4_cpu_m (arcache_dma_axi4_cpu_m),
  .arprot_dma_axi4_cpu_m (arprot_dma_axi4_cpu_m),
  .arvalid_dma_axi4_cpu_m (arvalid_dma_axi4_cpu_m),
  .arready_dma_axi4_cpu_m (arready_dma_axi4_cpu_m),
  .rid_dma_axi4_cpu_m   (rid_dma_axi4_cpu_m),
  .rdata_dma_axi4_cpu_m (rdata_dma_axi4_cpu_m),
  .rresp_dma_axi4_cpu_m (rresp_dma_axi4_cpu_m),
  .rlast_dma_axi4_cpu_m (rlast_dma_axi4_cpu_m),
  .rvalid_dma_axi4_cpu_m (rvalid_dma_axi4_cpu_m),
  .rready_dma_axi4_cpu_m (rready_dma_axi4_cpu_m),
  .awid_dma_axi4_cpu_s  (awid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awaddr_dma_axi4_cpu_s (awaddr_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awlen_dma_axi4_cpu_s (awlen_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awsize_dma_axi4_cpu_s (awsize_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awburst_dma_axi4_cpu_s (awburst_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awlock_dma_axi4_cpu_s (awlock_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awcache_dma_axi4_cpu_s (awcache_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awprot_dma_axi4_cpu_s (awprot_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awvalid_dma_axi4_cpu_s (awvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awready_dma_axi4_cpu_s (awready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wdata_dma_axi4_cpu_s (wdata_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wstrb_dma_axi4_cpu_s (wstrb_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wlast_dma_axi4_cpu_s (wlast_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wvalid_dma_axi4_cpu_s (wvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wready_dma_axi4_cpu_s (wready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bid_dma_axi4_cpu_s   (bid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bresp_dma_axi4_cpu_s (bresp_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bvalid_dma_axi4_cpu_s (bvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bready_dma_axi4_cpu_s (bready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arid_dma_axi4_cpu_s  (arid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .araddr_dma_axi4_cpu_s (araddr_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arlen_dma_axi4_cpu_s (arlen_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arsize_dma_axi4_cpu_s (arsize_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arburst_dma_axi4_cpu_s (arburst_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arlock_dma_axi4_cpu_s (arlock_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arcache_dma_axi4_cpu_s (arcache_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arprot_dma_axi4_cpu_s (arprot_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arvalid_dma_axi4_cpu_s (arvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arready_dma_axi4_cpu_s (arready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rid_dma_axi4_cpu_s   (rid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rdata_dma_axi4_cpu_s (rdata_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rresp_dma_axi4_cpu_s (rresp_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rlast_dma_axi4_cpu_s (rlast_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rvalid_dma_axi4_cpu_s (rvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rready_dma_axi4_cpu_s (rready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .aclk                 (clk_core_200_800mclk),
  .aresetn              (clk_core_200_800mresetn)
);


nic400_amib_sram_slv_axi4_ysyx_rv32     u_amib_sram_slv_axi4 (
  .awid_sram_slv_axi4_m (awid_sram_slv_axi4),
  .awaddr_sram_slv_axi4_m (awaddr_sram_slv_axi4),
  .awlen_sram_slv_axi4_m (awlen_sram_slv_axi4),
  .awsize_sram_slv_axi4_m (awsize_sram_slv_axi4),
  .awburst_sram_slv_axi4_m (awburst_sram_slv_axi4),
  .awlock_sram_slv_axi4_m (awlock_sram_slv_axi4),
  .awcache_sram_slv_axi4_m (awcache_sram_slv_axi4),
  .awprot_sram_slv_axi4_m (awprot_sram_slv_axi4),
  .awvalid_sram_slv_axi4_m (awvalid_sram_slv_axi4),
  .awready_sram_slv_axi4_m (awready_sram_slv_axi4),
  .wdata_sram_slv_axi4_m (wdata_sram_slv_axi4),
  .wstrb_sram_slv_axi4_m (wstrb_sram_slv_axi4),
  .wlast_sram_slv_axi4_m (wlast_sram_slv_axi4),
  .wvalid_sram_slv_axi4_m (wvalid_sram_slv_axi4),
  .wready_sram_slv_axi4_m (wready_sram_slv_axi4),
  .bid_sram_slv_axi4_m  (bid_sram_slv_axi4),
  .bresp_sram_slv_axi4_m (bresp_sram_slv_axi4),
  .bvalid_sram_slv_axi4_m (bvalid_sram_slv_axi4),
  .bready_sram_slv_axi4_m (bready_sram_slv_axi4),
  .arid_sram_slv_axi4_m (arid_sram_slv_axi4),
  .araddr_sram_slv_axi4_m (araddr_sram_slv_axi4),
  .arlen_sram_slv_axi4_m (arlen_sram_slv_axi4),
  .arsize_sram_slv_axi4_m (arsize_sram_slv_axi4),
  .arburst_sram_slv_axi4_m (arburst_sram_slv_axi4),
  .arlock_sram_slv_axi4_m (arlock_sram_slv_axi4),
  .arcache_sram_slv_axi4_m (arcache_sram_slv_axi4),
  .arprot_sram_slv_axi4_m (arprot_sram_slv_axi4),
  .arvalid_sram_slv_axi4_m (arvalid_sram_slv_axi4),
  .arready_sram_slv_axi4_m (arready_sram_slv_axi4),
  .rid_sram_slv_axi4_m  (rid_sram_slv_axi4),
  .rdata_sram_slv_axi4_m (rdata_sram_slv_axi4),
  .rresp_sram_slv_axi4_m (rresp_sram_slv_axi4),
  .rlast_sram_slv_axi4_m (rlast_sram_slv_axi4),
  .rvalid_sram_slv_axi4_m (rvalid_sram_slv_axi4),
  .rready_sram_slv_axi4_m (rready_sram_slv_axi4),
  .awid_sram_slv_axi4_s (awid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awaddr_sram_slv_axi4_s (awaddr_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awlen_sram_slv_axi4_s (awlen_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awsize_sram_slv_axi4_s (awsize_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awburst_sram_slv_axi4_s (awburst_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awlock_sram_slv_axi4_s (awlock_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awcache_sram_slv_axi4_s (awcache_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awprot_sram_slv_axi4_s (awprot_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awvalid_sram_slv_axi4_s (awvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awready_sram_slv_axi4_s (awready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wdata_sram_slv_axi4_s (wdata_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wstrb_sram_slv_axi4_s (wstrb_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wlast_sram_slv_axi4_s (wlast_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wvalid_sram_slv_axi4_s (wvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wready_sram_slv_axi4_s (wready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bid_sram_slv_axi4_s  (bid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bresp_sram_slv_axi4_s (bresp_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bvalid_sram_slv_axi4_s (bvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bready_sram_slv_axi4_s (bready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arid_sram_slv_axi4_s (arid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .araddr_sram_slv_axi4_s (araddr_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arlen_sram_slv_axi4_s (arlen_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arsize_sram_slv_axi4_s (arsize_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arburst_sram_slv_axi4_s (arburst_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arlock_sram_slv_axi4_s (arlock_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arcache_sram_slv_axi4_s (arcache_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arprot_sram_slv_axi4_s (arprot_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arvalid_sram_slv_axi4_s (arvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arready_sram_slv_axi4_s (arready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rid_sram_slv_axi4_s  (rid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rdata_sram_slv_axi4_s (rdata_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rresp_sram_slv_axi4_s (rresp_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rlast_sram_slv_axi4_s (rlast_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rvalid_sram_slv_axi4_s (rvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rready_sram_slv_axi4_s (rready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .aclk                 (clk_core_200_800mclk),
  .aresetn              (clk_core_200_800mresetn)
);


nic400_asib_cpu_mst_axi4_ysyx_rv32     u_asib_cpu_mst_axi4 (
  .awid_cpu_axi4_nic400_m (awid_cpu_mst_axi4_switch2_axi_s_0),
  .awaddr_cpu_axi4_nic400_m (awaddr_cpu_mst_axi4_switch2_axi_s_0),
  .awlen_cpu_axi4_nic400_m (awlen_cpu_mst_axi4_switch2_axi_s_0),
  .awsize_cpu_axi4_nic400_m (awsize_cpu_mst_axi4_switch2_axi_s_0),
  .awburst_cpu_axi4_nic400_m (awburst_cpu_mst_axi4_switch2_axi_s_0),
  .awlock_cpu_axi4_nic400_m (awlock_cpu_mst_axi4_switch2_axi_s_0),
  .awcache_cpu_axi4_nic400_m (awcache_cpu_mst_axi4_switch2_axi_s_0),
  .awprot_cpu_axi4_nic400_m (awprot_cpu_mst_axi4_switch2_axi_s_0),
  .awvalid_cpu_axi4_nic400_m (awvalid_cpu_mst_axi4_switch2_axi_s_0),
  .awvalid_vect_cpu_axi4_nic400_m (awvalid_vect_cpu_mst_axi4_switch2_axi_s_0),
  .awregion_cpu_axi4_nic400_m (awregion_cpu_mst_axi4_switch2_axi_s_0),
  .awready_cpu_axi4_nic400_m (awready_cpu_mst_axi4_switch2_axi_s_0),
  .wdata_cpu_axi4_nic400_m (wdata_cpu_mst_axi4_switch2_axi_s_0),
  .wstrb_cpu_axi4_nic400_m (wstrb_cpu_mst_axi4_switch2_axi_s_0),
  .wlast_cpu_axi4_nic400_m (wlast_cpu_mst_axi4_switch2_axi_s_0),
  .wvalid_cpu_axi4_nic400_m (wvalid_cpu_mst_axi4_switch2_axi_s_0),
  .wready_cpu_axi4_nic400_m (wready_cpu_mst_axi4_switch2_axi_s_0),
  .bid_cpu_axi4_nic400_m (bid_cpu_mst_axi4_switch2_axi_s_0),
  .bresp_cpu_axi4_nic400_m (bresp_cpu_mst_axi4_switch2_axi_s_0),
  .bvalid_cpu_axi4_nic400_m (bvalid_cpu_mst_axi4_switch2_axi_s_0),
  .bready_cpu_axi4_nic400_m (bready_cpu_mst_axi4_switch2_axi_s_0),
  .arid_cpu_axi4_nic400_m (arid_cpu_mst_axi4_switch2_axi_s_0),
  .araddr_cpu_axi4_nic400_m (araddr_cpu_mst_axi4_switch2_axi_s_0),
  .arlen_cpu_axi4_nic400_m (arlen_cpu_mst_axi4_switch2_axi_s_0),
  .arsize_cpu_axi4_nic400_m (arsize_cpu_mst_axi4_switch2_axi_s_0),
  .arburst_cpu_axi4_nic400_m (arburst_cpu_mst_axi4_switch2_axi_s_0),
  .arlock_cpu_axi4_nic400_m (arlock_cpu_mst_axi4_switch2_axi_s_0),
  .arcache_cpu_axi4_nic400_m (arcache_cpu_mst_axi4_switch2_axi_s_0),
  .arprot_cpu_axi4_nic400_m (arprot_cpu_mst_axi4_switch2_axi_s_0),
  .arvalid_cpu_axi4_nic400_m (arvalid_cpu_mst_axi4_switch2_axi_s_0),
  .arvalid_vect_cpu_axi4_nic400_m (arvalid_vect_cpu_mst_axi4_switch2_axi_s_0),
  .arregion_cpu_axi4_nic400_m (arregion_cpu_mst_axi4_switch2_axi_s_0),
  .arready_cpu_axi4_nic400_m (arready_cpu_mst_axi4_switch2_axi_s_0),
  .rid_cpu_axi4_nic400_m (rid_cpu_mst_axi4_switch2_axi_s_0),
  .rdata_cpu_axi4_nic400_m (rdata_cpu_mst_axi4_switch2_axi_s_0),
  .rresp_cpu_axi4_nic400_m (rresp_cpu_mst_axi4_switch2_axi_s_0),
  .rlast_cpu_axi4_nic400_m (rlast_cpu_mst_axi4_switch2_axi_s_0),
  .rvalid_cpu_axi4_nic400_m (rvalid_cpu_mst_axi4_switch2_axi_s_0),
  .rready_cpu_axi4_nic400_m (rready_cpu_mst_axi4_switch2_axi_s_0),
  .awqv_cpu_axi4_nic400_m (awqv_cpu_mst_axi4_switch2_axi_s_0),
  .arqv_cpu_axi4_nic400_m (arqv_cpu_mst_axi4_switch2_axi_s_0),
  .aclk                 (clk_core_200_800mclk),
  .aresetn              (clk_core_200_800mresetn),
  .awid_cpu_mst_axi4_s  (awid_cpu_mst_axi4),
  .awaddr_cpu_mst_axi4_s (awaddr_cpu_mst_axi4),
  .awlen_cpu_mst_axi4_s (awlen_cpu_mst_axi4),
  .awsize_cpu_mst_axi4_s (awsize_cpu_mst_axi4),
  .awburst_cpu_mst_axi4_s (awburst_cpu_mst_axi4),
  .awlock_cpu_mst_axi4_s (awlock_cpu_mst_axi4),
  .awcache_cpu_mst_axi4_s (awcache_cpu_mst_axi4),
  .awprot_cpu_mst_axi4_s (awprot_cpu_mst_axi4),
  .awvalid_cpu_mst_axi4_s (awvalid_cpu_mst_axi4),
  .awready_cpu_mst_axi4_s (awready_cpu_mst_axi4),
  .wdata_cpu_mst_axi4_s (wdata_cpu_mst_axi4),
  .wstrb_cpu_mst_axi4_s (wstrb_cpu_mst_axi4),
  .wlast_cpu_mst_axi4_s (wlast_cpu_mst_axi4),
  .wvalid_cpu_mst_axi4_s (wvalid_cpu_mst_axi4),
  .wready_cpu_mst_axi4_s (wready_cpu_mst_axi4),
  .bid_cpu_mst_axi4_s   (bid_cpu_mst_axi4),
  .bresp_cpu_mst_axi4_s (bresp_cpu_mst_axi4),
  .bvalid_cpu_mst_axi4_s (bvalid_cpu_mst_axi4),
  .bready_cpu_mst_axi4_s (bready_cpu_mst_axi4),
  .arid_cpu_mst_axi4_s  (arid_cpu_mst_axi4),
  .araddr_cpu_mst_axi4_s (araddr_cpu_mst_axi4),
  .arlen_cpu_mst_axi4_s (arlen_cpu_mst_axi4),
  .arsize_cpu_mst_axi4_s (arsize_cpu_mst_axi4),
  .arburst_cpu_mst_axi4_s (arburst_cpu_mst_axi4),
  .arlock_cpu_mst_axi4_s (arlock_cpu_mst_axi4),
  .arcache_cpu_mst_axi4_s (arcache_cpu_mst_axi4),
  .arprot_cpu_mst_axi4_s (arprot_cpu_mst_axi4),
  .arvalid_cpu_mst_axi4_s (arvalid_cpu_mst_axi4),
  .arready_cpu_mst_axi4_s (arready_cpu_mst_axi4),
  .rid_cpu_mst_axi4_s   (rid_cpu_mst_axi4),
  .rdata_cpu_mst_axi4_s (rdata_cpu_mst_axi4),
  .rresp_cpu_mst_axi4_s (rresp_cpu_mst_axi4),
  .rlast_cpu_mst_axi4_s (rlast_cpu_mst_axi4),
  .rvalid_cpu_mst_axi4_s (rvalid_cpu_mst_axi4),
  .rready_cpu_mst_axi4_s (rready_cpu_mst_axi4)
);


nic400_switch2_ysyx_rv32     u_busmatrix_switch2 (
  .awid_axi_m_0         (awid_switch2_sram_slv_axi4_ib_axi4_s),
  .awaddr_axi_m_0       (awaddr_switch2_sram_slv_axi4_ib_axi4_s),
  .awlen_axi_m_0        (awlen_switch2_sram_slv_axi4_ib_axi4_s),
  .awsize_axi_m_0       (awsize_switch2_sram_slv_axi4_ib_axi4_s),
  .awburst_axi_m_0      (awburst_switch2_sram_slv_axi4_ib_axi4_s),
  .awlock_axi_m_0       (awlock_switch2_sram_slv_axi4_ib_axi4_s),
  .awcache_axi_m_0      (awcache_switch2_sram_slv_axi4_ib_axi4_s),
  .awprot_axi_m_0       (awprot_switch2_sram_slv_axi4_ib_axi4_s),
  .awregion_axi_m_0     (awregion_switch2_sram_slv_axi4_ib_axi4_s),
  .awvalid_axi_m_0      (awvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .awvalid_vect_axi_m_0 (),
  .awready_axi_m_0      (awready_switch2_sram_slv_axi4_ib_axi4_s),
  .wdata_axi_m_0        (wdata_switch2_sram_slv_axi4_ib_axi4_s),
  .wstrb_axi_m_0        (wstrb_switch2_sram_slv_axi4_ib_axi4_s),
  .wlast_axi_m_0        (wlast_switch2_sram_slv_axi4_ib_axi4_s),
  .wvalid_axi_m_0       (wvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .wready_axi_m_0       (wready_switch2_sram_slv_axi4_ib_axi4_s),
  .bid_axi_m_0          (bid_switch2_sram_slv_axi4_ib_axi4_s),
  .bresp_axi_m_0        (bresp_switch2_sram_slv_axi4_ib_axi4_s),
  .bvalid_axi_m_0       (bvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .bready_axi_m_0       (bready_switch2_sram_slv_axi4_ib_axi4_s),
  .arid_axi_m_0         (arid_switch2_sram_slv_axi4_ib_axi4_s),
  .araddr_axi_m_0       (araddr_switch2_sram_slv_axi4_ib_axi4_s),
  .arlen_axi_m_0        (arlen_switch2_sram_slv_axi4_ib_axi4_s),
  .arsize_axi_m_0       (arsize_switch2_sram_slv_axi4_ib_axi4_s),
  .arburst_axi_m_0      (arburst_switch2_sram_slv_axi4_ib_axi4_s),
  .arlock_axi_m_0       (arlock_switch2_sram_slv_axi4_ib_axi4_s),
  .arcache_axi_m_0      (arcache_switch2_sram_slv_axi4_ib_axi4_s),
  .arprot_axi_m_0       (arprot_switch2_sram_slv_axi4_ib_axi4_s),
  .arregion_axi_m_0     (arregion_switch2_sram_slv_axi4_ib_axi4_s),
  .arvalid_axi_m_0      (arvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .arvalid_vect_axi_m_0 (),
  .arready_axi_m_0      (arready_switch2_sram_slv_axi4_ib_axi4_s),
  .rid_axi_m_0          (rid_switch2_sram_slv_axi4_ib_axi4_s),
  .rdata_axi_m_0        (rdata_switch2_sram_slv_axi4_ib_axi4_s),
  .rresp_axi_m_0        (rresp_switch2_sram_slv_axi4_ib_axi4_s),
  .rlast_axi_m_0        (rlast_switch2_sram_slv_axi4_ib_axi4_s),
  .rvalid_axi_m_0       (rvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .rready_axi_m_0       (rready_switch2_sram_slv_axi4_ib_axi4_s),
  .aw_qv_axi_m_0        (),
  .ar_qv_axi_m_0        (),
  .awid_axi_m_1         (awid_switch2_perip0_gp_apb4_ib_axi4_s),
  .awaddr_axi_m_1       (awaddr_switch2_perip0_gp_apb4_ib_axi4_s),
  .awlen_axi_m_1        (awlen_switch2_perip0_gp_apb4_ib_axi4_s),
  .awsize_axi_m_1       (awsize_switch2_perip0_gp_apb4_ib_axi4_s),
  .awburst_axi_m_1      (awburst_switch2_perip0_gp_apb4_ib_axi4_s),
  .awlock_axi_m_1       (awlock_switch2_perip0_gp_apb4_ib_axi4_s),
  .awcache_axi_m_1      (awcache_switch2_perip0_gp_apb4_ib_axi4_s),
  .awprot_axi_m_1       (awprot_switch2_perip0_gp_apb4_ib_axi4_s),
  .awregion_axi_m_1     (awregion_switch2_perip0_gp_apb4_ib_axi4_s),
  .awvalid_axi_m_1      (awvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .awvalid_vect_axi_m_1 (),
  .awready_axi_m_1      (awready_switch2_perip0_gp_apb4_ib_axi4_s),
  .wdata_axi_m_1        (wdata_switch2_perip0_gp_apb4_ib_axi4_s),
  .wstrb_axi_m_1        (wstrb_switch2_perip0_gp_apb4_ib_axi4_s),
  .wlast_axi_m_1        (wlast_switch2_perip0_gp_apb4_ib_axi4_s),
  .wvalid_axi_m_1       (wvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .wready_axi_m_1       (wready_switch2_perip0_gp_apb4_ib_axi4_s),
  .bid_axi_m_1          (bid_switch2_perip0_gp_apb4_ib_axi4_s),
  .bresp_axi_m_1        (bresp_switch2_perip0_gp_apb4_ib_axi4_s),
  .bvalid_axi_m_1       (bvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .bready_axi_m_1       (bready_switch2_perip0_gp_apb4_ib_axi4_s),
  .arid_axi_m_1         (arid_switch2_perip0_gp_apb4_ib_axi4_s),
  .araddr_axi_m_1       (araddr_switch2_perip0_gp_apb4_ib_axi4_s),
  .arlen_axi_m_1        (arlen_switch2_perip0_gp_apb4_ib_axi4_s),
  .arsize_axi_m_1       (arsize_switch2_perip0_gp_apb4_ib_axi4_s),
  .arburst_axi_m_1      (arburst_switch2_perip0_gp_apb4_ib_axi4_s),
  .arlock_axi_m_1       (arlock_switch2_perip0_gp_apb4_ib_axi4_s),
  .arcache_axi_m_1      (arcache_switch2_perip0_gp_apb4_ib_axi4_s),
  .arprot_axi_m_1       (arprot_switch2_perip0_gp_apb4_ib_axi4_s),
  .arregion_axi_m_1     (arregion_switch2_perip0_gp_apb4_ib_axi4_s),
  .arvalid_axi_m_1      (arvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .arvalid_vect_axi_m_1 (),
  .arready_axi_m_1      (arready_switch2_perip0_gp_apb4_ib_axi4_s),
  .rid_axi_m_1          (rid_switch2_perip0_gp_apb4_ib_axi4_s),
  .rdata_axi_m_1        (rdata_switch2_perip0_gp_apb4_ib_axi4_s),
  .rresp_axi_m_1        (rresp_switch2_perip0_gp_apb4_ib_axi4_s),
  .rlast_axi_m_1        (rlast_switch2_perip0_gp_apb4_ib_axi4_s),
  .rvalid_axi_m_1       (rvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .rready_axi_m_1       (rready_switch2_perip0_gp_apb4_ib_axi4_s),
  .aw_qv_axi_m_1        (),
  .ar_qv_axi_m_1        (),
  .awid_axi_m_2         (awid_switch2_ds_1_axi_s_0),
  .awaddr_axi_m_2       (),
  .awlen_axi_m_2        (),
  .awsize_axi_m_2       (),
  .awburst_axi_m_2      (),
  .awlock_axi_m_2       (),
  .awcache_axi_m_2      (),
  .awprot_axi_m_2       (),
  .awregion_axi_m_2     (),
  .awvalid_axi_m_2      (awvalid_switch2_ds_1_axi_s_0),
  .awvalid_vect_axi_m_2 (),
  .awready_axi_m_2      (awready_switch2_ds_1_axi_s_0),
  .wdata_axi_m_2        (),
  .wstrb_axi_m_2        (),
  .wlast_axi_m_2        (wlast_switch2_ds_1_axi_s_0),
  .wvalid_axi_m_2       (wvalid_switch2_ds_1_axi_s_0),
  .wready_axi_m_2       (wready_switch2_ds_1_axi_s_0),
  .bid_axi_m_2          (bid_switch2_ds_1_axi_s_0),
  .bresp_axi_m_2        (bresp_switch2_ds_1_axi_s_0),
  .bvalid_axi_m_2       (bvalid_switch2_ds_1_axi_s_0),
  .bready_axi_m_2       (bready_switch2_ds_1_axi_s_0),
  .arid_axi_m_2         (arid_switch2_ds_1_axi_s_0),
  .araddr_axi_m_2       (),
  .arlen_axi_m_2        (arlen_switch2_ds_1_axi_s_0),
  .arsize_axi_m_2       (),
  .arburst_axi_m_2      (),
  .arlock_axi_m_2       (),
  .arcache_axi_m_2      (),
  .arprot_axi_m_2       (),
  .arregion_axi_m_2     (),
  .arvalid_axi_m_2      (arvalid_switch2_ds_1_axi_s_0),
  .arvalid_vect_axi_m_2 (),
  .arready_axi_m_2      (arready_switch2_ds_1_axi_s_0),
  .rid_axi_m_2          (rid_switch2_ds_1_axi_s_0),
  .rdata_axi_m_2        (32'b0),
  .rresp_axi_m_2        (rresp_switch2_ds_1_axi_s_0),
  .rlast_axi_m_2        (rlast_switch2_ds_1_axi_s_0),
  .rvalid_axi_m_2       (rvalid_switch2_ds_1_axi_s_0),
  .rready_axi_m_2       (rready_switch2_ds_1_axi_s_0),
  .aw_qv_axi_m_2        (),
  .ar_qv_axi_m_2        (),
  .awid_axi_m_4         (awid_switch2_perip1_gp_apb4_ib_axi4_s),
  .awaddr_axi_m_4       (awaddr_switch2_perip1_gp_apb4_ib_axi4_s),
  .awlen_axi_m_4        (awlen_switch2_perip1_gp_apb4_ib_axi4_s),
  .awsize_axi_m_4       (awsize_switch2_perip1_gp_apb4_ib_axi4_s),
  .awburst_axi_m_4      (awburst_switch2_perip1_gp_apb4_ib_axi4_s),
  .awlock_axi_m_4       (awlock_switch2_perip1_gp_apb4_ib_axi4_s),
  .awcache_axi_m_4      (awcache_switch2_perip1_gp_apb4_ib_axi4_s),
  .awprot_axi_m_4       (awprot_switch2_perip1_gp_apb4_ib_axi4_s),
  .awregion_axi_m_4     (awregion_switch2_perip1_gp_apb4_ib_axi4_s),
  .awvalid_axi_m_4      (awvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .awvalid_vect_axi_m_4 (),
  .awready_axi_m_4      (awready_switch2_perip1_gp_apb4_ib_axi4_s),
  .wdata_axi_m_4        (wdata_switch2_perip1_gp_apb4_ib_axi4_s),
  .wstrb_axi_m_4        (wstrb_switch2_perip1_gp_apb4_ib_axi4_s),
  .wlast_axi_m_4        (wlast_switch2_perip1_gp_apb4_ib_axi4_s),
  .wvalid_axi_m_4       (wvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .wready_axi_m_4       (wready_switch2_perip1_gp_apb4_ib_axi4_s),
  .bid_axi_m_4          (bid_switch2_perip1_gp_apb4_ib_axi4_s),
  .bresp_axi_m_4        (bresp_switch2_perip1_gp_apb4_ib_axi4_s),
  .bvalid_axi_m_4       (bvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .bready_axi_m_4       (bready_switch2_perip1_gp_apb4_ib_axi4_s),
  .arid_axi_m_4         (arid_switch2_perip1_gp_apb4_ib_axi4_s),
  .araddr_axi_m_4       (araddr_switch2_perip1_gp_apb4_ib_axi4_s),
  .arlen_axi_m_4        (arlen_switch2_perip1_gp_apb4_ib_axi4_s),
  .arsize_axi_m_4       (arsize_switch2_perip1_gp_apb4_ib_axi4_s),
  .arburst_axi_m_4      (arburst_switch2_perip1_gp_apb4_ib_axi4_s),
  .arlock_axi_m_4       (arlock_switch2_perip1_gp_apb4_ib_axi4_s),
  .arcache_axi_m_4      (arcache_switch2_perip1_gp_apb4_ib_axi4_s),
  .arprot_axi_m_4       (arprot_switch2_perip1_gp_apb4_ib_axi4_s),
  .arregion_axi_m_4     (arregion_switch2_perip1_gp_apb4_ib_axi4_s),
  .arvalid_axi_m_4      (arvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .arvalid_vect_axi_m_4 (),
  .arready_axi_m_4      (arready_switch2_perip1_gp_apb4_ib_axi4_s),
  .rid_axi_m_4          (rid_switch2_perip1_gp_apb4_ib_axi4_s),
  .rdata_axi_m_4        (rdata_switch2_perip1_gp_apb4_ib_axi4_s),
  .rresp_axi_m_4        (rresp_switch2_perip1_gp_apb4_ib_axi4_s),
  .rlast_axi_m_4        (rlast_switch2_perip1_gp_apb4_ib_axi4_s),
  .rvalid_axi_m_4       (rvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .rready_axi_m_4       (rready_switch2_perip1_gp_apb4_ib_axi4_s),
  .aw_qv_axi_m_4        (),
  .ar_qv_axi_m_4        (),
  .aclk                 (clk_core_200_800mclk),
  .aresetn              (clk_core_200_800mresetn),
  .awid_axi_m_5         (awid_switch2_psram_slv_axi4_ib_axi4_s),
  .awaddr_axi_m_5       (awaddr_switch2_psram_slv_axi4_ib_axi4_s),
  .awlen_axi_m_5        (awlen_switch2_psram_slv_axi4_ib_axi4_s),
  .awsize_axi_m_5       (awsize_switch2_psram_slv_axi4_ib_axi4_s),
  .awburst_axi_m_5      (awburst_switch2_psram_slv_axi4_ib_axi4_s),
  .awlock_axi_m_5       (awlock_switch2_psram_slv_axi4_ib_axi4_s),
  .awcache_axi_m_5      (awcache_switch2_psram_slv_axi4_ib_axi4_s),
  .awprot_axi_m_5       (awprot_switch2_psram_slv_axi4_ib_axi4_s),
  .awregion_axi_m_5     (awregion_switch2_psram_slv_axi4_ib_axi4_s),
  .awvalid_axi_m_5      (awvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .awvalid_vect_axi_m_5 (),
  .awready_axi_m_5      (awready_switch2_psram_slv_axi4_ib_axi4_s),
  .wdata_axi_m_5        (wdata_switch2_psram_slv_axi4_ib_axi4_s),
  .wstrb_axi_m_5        (wstrb_switch2_psram_slv_axi4_ib_axi4_s),
  .wlast_axi_m_5        (wlast_switch2_psram_slv_axi4_ib_axi4_s),
  .wvalid_axi_m_5       (wvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .wready_axi_m_5       (wready_switch2_psram_slv_axi4_ib_axi4_s),
  .bid_axi_m_5          (bid_switch2_psram_slv_axi4_ib_axi4_s),
  .bresp_axi_m_5        (bresp_switch2_psram_slv_axi4_ib_axi4_s),
  .bvalid_axi_m_5       (bvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .bready_axi_m_5       (bready_switch2_psram_slv_axi4_ib_axi4_s),
  .arid_axi_m_5         (arid_switch2_psram_slv_axi4_ib_axi4_s),
  .araddr_axi_m_5       (araddr_switch2_psram_slv_axi4_ib_axi4_s),
  .arlen_axi_m_5        (arlen_switch2_psram_slv_axi4_ib_axi4_s),
  .arsize_axi_m_5       (arsize_switch2_psram_slv_axi4_ib_axi4_s),
  .arburst_axi_m_5      (arburst_switch2_psram_slv_axi4_ib_axi4_s),
  .arlock_axi_m_5       (arlock_switch2_psram_slv_axi4_ib_axi4_s),
  .arcache_axi_m_5      (arcache_switch2_psram_slv_axi4_ib_axi4_s),
  .arprot_axi_m_5       (arprot_switch2_psram_slv_axi4_ib_axi4_s),
  .arregion_axi_m_5     (arregion_switch2_psram_slv_axi4_ib_axi4_s),
  .arvalid_axi_m_5      (arvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .arvalid_vect_axi_m_5 (),
  .arready_axi_m_5      (arready_switch2_psram_slv_axi4_ib_axi4_s),
  .rid_axi_m_5          (rid_switch2_psram_slv_axi4_ib_axi4_s),
  .rdata_axi_m_5        (rdata_switch2_psram_slv_axi4_ib_axi4_s),
  .rresp_axi_m_5        (rresp_switch2_psram_slv_axi4_ib_axi4_s),
  .rlast_axi_m_5        (rlast_switch2_psram_slv_axi4_ib_axi4_s),
  .rvalid_axi_m_5       (rvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .rready_axi_m_5       (rready_switch2_psram_slv_axi4_ib_axi4_s),
  .aw_qv_axi_m_5        (),
  .ar_qv_axi_m_5        (),
  .awid_axi_m_6         (awid_switch2_sdram_slv_axi4_ib_axi4_s),
  .awaddr_axi_m_6       (awaddr_switch2_sdram_slv_axi4_ib_axi4_s),
  .awlen_axi_m_6        (awlen_switch2_sdram_slv_axi4_ib_axi4_s),
  .awsize_axi_m_6       (awsize_switch2_sdram_slv_axi4_ib_axi4_s),
  .awburst_axi_m_6      (awburst_switch2_sdram_slv_axi4_ib_axi4_s),
  .awlock_axi_m_6       (awlock_switch2_sdram_slv_axi4_ib_axi4_s),
  .awcache_axi_m_6      (awcache_switch2_sdram_slv_axi4_ib_axi4_s),
  .awprot_axi_m_6       (awprot_switch2_sdram_slv_axi4_ib_axi4_s),
  .awregion_axi_m_6     (awregion_switch2_sdram_slv_axi4_ib_axi4_s),
  .awvalid_axi_m_6      (awvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .awvalid_vect_axi_m_6 (),
  .awready_axi_m_6      (awready_switch2_sdram_slv_axi4_ib_axi4_s),
  .wdata_axi_m_6        (wdata_switch2_sdram_slv_axi4_ib_axi4_s),
  .wstrb_axi_m_6        (wstrb_switch2_sdram_slv_axi4_ib_axi4_s),
  .wlast_axi_m_6        (wlast_switch2_sdram_slv_axi4_ib_axi4_s),
  .wvalid_axi_m_6       (wvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .wready_axi_m_6       (wready_switch2_sdram_slv_axi4_ib_axi4_s),
  .bid_axi_m_6          (bid_switch2_sdram_slv_axi4_ib_axi4_s),
  .bresp_axi_m_6        (bresp_switch2_sdram_slv_axi4_ib_axi4_s),
  .bvalid_axi_m_6       (bvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .bready_axi_m_6       (bready_switch2_sdram_slv_axi4_ib_axi4_s),
  .arid_axi_m_6         (arid_switch2_sdram_slv_axi4_ib_axi4_s),
  .araddr_axi_m_6       (araddr_switch2_sdram_slv_axi4_ib_axi4_s),
  .arlen_axi_m_6        (arlen_switch2_sdram_slv_axi4_ib_axi4_s),
  .arsize_axi_m_6       (arsize_switch2_sdram_slv_axi4_ib_axi4_s),
  .arburst_axi_m_6      (arburst_switch2_sdram_slv_axi4_ib_axi4_s),
  .arlock_axi_m_6       (arlock_switch2_sdram_slv_axi4_ib_axi4_s),
  .arcache_axi_m_6      (arcache_switch2_sdram_slv_axi4_ib_axi4_s),
  .arprot_axi_m_6       (arprot_switch2_sdram_slv_axi4_ib_axi4_s),
  .arregion_axi_m_6     (arregion_switch2_sdram_slv_axi4_ib_axi4_s),
  .arvalid_axi_m_6      (arvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .arvalid_vect_axi_m_6 (),
  .arready_axi_m_6      (arready_switch2_sdram_slv_axi4_ib_axi4_s),
  .rid_axi_m_6          (rid_switch2_sdram_slv_axi4_ib_axi4_s),
  .rdata_axi_m_6        (rdata_switch2_sdram_slv_axi4_ib_axi4_s),
  .rresp_axi_m_6        (rresp_switch2_sdram_slv_axi4_ib_axi4_s),
  .rlast_axi_m_6        (rlast_switch2_sdram_slv_axi4_ib_axi4_s),
  .rvalid_axi_m_6       (rvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .rready_axi_m_6       (rready_switch2_sdram_slv_axi4_ib_axi4_s),
  .aw_qv_axi_m_6        (),
  .ar_qv_axi_m_6        (),
  .awid_axi_m_7         (awid_switch2_tpv_gp_apb4_ib_axi4_s),
  .awaddr_axi_m_7       (awaddr_switch2_tpv_gp_apb4_ib_axi4_s),
  .awlen_axi_m_7        (awlen_switch2_tpv_gp_apb4_ib_axi4_s),
  .awsize_axi_m_7       (awsize_switch2_tpv_gp_apb4_ib_axi4_s),
  .awburst_axi_m_7      (awburst_switch2_tpv_gp_apb4_ib_axi4_s),
  .awlock_axi_m_7       (awlock_switch2_tpv_gp_apb4_ib_axi4_s),
  .awcache_axi_m_7      (awcache_switch2_tpv_gp_apb4_ib_axi4_s),
  .awprot_axi_m_7       (awprot_switch2_tpv_gp_apb4_ib_axi4_s),
  .awregion_axi_m_7     (awregion_switch2_tpv_gp_apb4_ib_axi4_s),
  .awvalid_axi_m_7      (awvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .awvalid_vect_axi_m_7 (),
  .awready_axi_m_7      (awready_switch2_tpv_gp_apb4_ib_axi4_s),
  .wdata_axi_m_7        (wdata_switch2_tpv_gp_apb4_ib_axi4_s),
  .wstrb_axi_m_7        (wstrb_switch2_tpv_gp_apb4_ib_axi4_s),
  .wlast_axi_m_7        (wlast_switch2_tpv_gp_apb4_ib_axi4_s),
  .wvalid_axi_m_7       (wvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .wready_axi_m_7       (wready_switch2_tpv_gp_apb4_ib_axi4_s),
  .bid_axi_m_7          (bid_switch2_tpv_gp_apb4_ib_axi4_s),
  .bresp_axi_m_7        (bresp_switch2_tpv_gp_apb4_ib_axi4_s),
  .bvalid_axi_m_7       (bvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .bready_axi_m_7       (bready_switch2_tpv_gp_apb4_ib_axi4_s),
  .arid_axi_m_7         (arid_switch2_tpv_gp_apb4_ib_axi4_s),
  .araddr_axi_m_7       (araddr_switch2_tpv_gp_apb4_ib_axi4_s),
  .arlen_axi_m_7        (arlen_switch2_tpv_gp_apb4_ib_axi4_s),
  .arsize_axi_m_7       (arsize_switch2_tpv_gp_apb4_ib_axi4_s),
  .arburst_axi_m_7      (arburst_switch2_tpv_gp_apb4_ib_axi4_s),
  .arlock_axi_m_7       (arlock_switch2_tpv_gp_apb4_ib_axi4_s),
  .arcache_axi_m_7      (arcache_switch2_tpv_gp_apb4_ib_axi4_s),
  .arprot_axi_m_7       (arprot_switch2_tpv_gp_apb4_ib_axi4_s),
  .arregion_axi_m_7     (arregion_switch2_tpv_gp_apb4_ib_axi4_s),
  .arvalid_axi_m_7      (arvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .arvalid_vect_axi_m_7 (),
  .arready_axi_m_7      (arready_switch2_tpv_gp_apb4_ib_axi4_s),
  .rid_axi_m_7          (rid_switch2_tpv_gp_apb4_ib_axi4_s),
  .rdata_axi_m_7        (rdata_switch2_tpv_gp_apb4_ib_axi4_s),
  .rresp_axi_m_7        (rresp_switch2_tpv_gp_apb4_ib_axi4_s),
  .rlast_axi_m_7        (rlast_switch2_tpv_gp_apb4_ib_axi4_s),
  .rvalid_axi_m_7       (rvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .rready_axi_m_7       (rready_switch2_tpv_gp_apb4_ib_axi4_s),
  .aw_qv_axi_m_7        (),
  .ar_qv_axi_m_7        (),
  .awid_axi_m_8         (awid_switch2_sys_gp_apb4_ib_axi4_s),
  .awaddr_axi_m_8       (awaddr_switch2_sys_gp_apb4_ib_axi4_s),
  .awlen_axi_m_8        (awlen_switch2_sys_gp_apb4_ib_axi4_s),
  .awsize_axi_m_8       (awsize_switch2_sys_gp_apb4_ib_axi4_s),
  .awburst_axi_m_8      (awburst_switch2_sys_gp_apb4_ib_axi4_s),
  .awlock_axi_m_8       (awlock_switch2_sys_gp_apb4_ib_axi4_s),
  .awcache_axi_m_8      (awcache_switch2_sys_gp_apb4_ib_axi4_s),
  .awprot_axi_m_8       (awprot_switch2_sys_gp_apb4_ib_axi4_s),
  .awregion_axi_m_8     (awregion_switch2_sys_gp_apb4_ib_axi4_s),
  .awvalid_axi_m_8      (awvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .awvalid_vect_axi_m_8 (),
  .awready_axi_m_8      (awready_switch2_sys_gp_apb4_ib_axi4_s),
  .wdata_axi_m_8        (wdata_switch2_sys_gp_apb4_ib_axi4_s),
  .wstrb_axi_m_8        (wstrb_switch2_sys_gp_apb4_ib_axi4_s),
  .wlast_axi_m_8        (wlast_switch2_sys_gp_apb4_ib_axi4_s),
  .wvalid_axi_m_8       (wvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .wready_axi_m_8       (wready_switch2_sys_gp_apb4_ib_axi4_s),
  .bid_axi_m_8          (bid_switch2_sys_gp_apb4_ib_axi4_s),
  .bresp_axi_m_8        (bresp_switch2_sys_gp_apb4_ib_axi4_s),
  .bvalid_axi_m_8       (bvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .bready_axi_m_8       (bready_switch2_sys_gp_apb4_ib_axi4_s),
  .arid_axi_m_8         (arid_switch2_sys_gp_apb4_ib_axi4_s),
  .araddr_axi_m_8       (araddr_switch2_sys_gp_apb4_ib_axi4_s),
  .arlen_axi_m_8        (arlen_switch2_sys_gp_apb4_ib_axi4_s),
  .arsize_axi_m_8       (arsize_switch2_sys_gp_apb4_ib_axi4_s),
  .arburst_axi_m_8      (arburst_switch2_sys_gp_apb4_ib_axi4_s),
  .arlock_axi_m_8       (arlock_switch2_sys_gp_apb4_ib_axi4_s),
  .arcache_axi_m_8      (arcache_switch2_sys_gp_apb4_ib_axi4_s),
  .arprot_axi_m_8       (arprot_switch2_sys_gp_apb4_ib_axi4_s),
  .arregion_axi_m_8     (arregion_switch2_sys_gp_apb4_ib_axi4_s),
  .arvalid_axi_m_8      (arvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .arvalid_vect_axi_m_8 (),
  .arready_axi_m_8      (arready_switch2_sys_gp_apb4_ib_axi4_s),
  .rid_axi_m_8          (rid_switch2_sys_gp_apb4_ib_axi4_s),
  .rdata_axi_m_8        (rdata_switch2_sys_gp_apb4_ib_axi4_s),
  .rresp_axi_m_8        (rresp_switch2_sys_gp_apb4_ib_axi4_s),
  .rlast_axi_m_8        (rlast_switch2_sys_gp_apb4_ib_axi4_s),
  .rvalid_axi_m_8       (rvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .rready_axi_m_8       (rready_switch2_sys_gp_apb4_ib_axi4_s),
  .aw_qv_axi_m_8        (),
  .ar_qv_axi_m_8        (),
  .awid_axi_m_9         (awid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awaddr_axi_m_9       (awaddr_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awlen_axi_m_9        (awlen_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awsize_axi_m_9       (awsize_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awburst_axi_m_9      (awburst_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awlock_axi_m_9       (awlock_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awcache_axi_m_9      (awcache_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awprot_axi_m_9       (awprot_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awregion_axi_m_9     (awregion_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awvalid_axi_m_9      (awvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awvalid_vect_axi_m_9 (),
  .awready_axi_m_9      (awready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wdata_axi_m_9        (wdata_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wstrb_axi_m_9        (wstrb_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wlast_axi_m_9        (wlast_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wvalid_axi_m_9       (wvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wready_axi_m_9       (wready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bid_axi_m_9          (bid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bresp_axi_m_9        (bresp_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bvalid_axi_m_9       (bvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bready_axi_m_9       (bready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arid_axi_m_9         (arid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .araddr_axi_m_9       (araddr_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arlen_axi_m_9        (arlen_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arsize_axi_m_9       (arsize_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arburst_axi_m_9      (arburst_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arlock_axi_m_9       (arlock_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arcache_axi_m_9      (arcache_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arprot_axi_m_9       (arprot_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arregion_axi_m_9     (arregion_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arvalid_axi_m_9      (arvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arvalid_vect_axi_m_9 (),
  .arready_axi_m_9      (arready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rid_axi_m_9          (rid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rdata_axi_m_9        (rdata_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rresp_axi_m_9        (rresp_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rlast_axi_m_9        (rlast_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rvalid_axi_m_9       (rvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rready_axi_m_9       (rready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .aw_qv_axi_m_9        (),
  .ar_qv_axi_m_9        (),
  .awid_axi_s_0         (awid_cpu_mst_axi4_switch2_axi_s_0),
  .awaddr_axi_s_0       (awaddr_cpu_mst_axi4_switch2_axi_s_0),
  .awlen_axi_s_0        (awlen_cpu_mst_axi4_switch2_axi_s_0),
  .awsize_axi_s_0       (awsize_cpu_mst_axi4_switch2_axi_s_0),
  .awburst_axi_s_0      (awburst_cpu_mst_axi4_switch2_axi_s_0),
  .awlock_axi_s_0       (awlock_cpu_mst_axi4_switch2_axi_s_0),
  .awcache_axi_s_0      (awcache_cpu_mst_axi4_switch2_axi_s_0),
  .awprot_axi_s_0       (awprot_cpu_mst_axi4_switch2_axi_s_0),
  .awregion_axi_s_0     (awregion_cpu_mst_axi4_switch2_axi_s_0),
  .awvalid_axi_s_0      (awvalid_cpu_mst_axi4_switch2_axi_s_0),
  .awvalid_vect_axi_s_0 (awvalid_vect_cpu_mst_axi4_switch2_axi_s_0),
  .awready_axi_s_0      (awready_cpu_mst_axi4_switch2_axi_s_0),
  .wdata_axi_s_0        (wdata_cpu_mst_axi4_switch2_axi_s_0),
  .wstrb_axi_s_0        (wstrb_cpu_mst_axi4_switch2_axi_s_0),
  .wlast_axi_s_0        (wlast_cpu_mst_axi4_switch2_axi_s_0),
  .wvalid_axi_s_0       (wvalid_cpu_mst_axi4_switch2_axi_s_0),
  .wready_axi_s_0       (wready_cpu_mst_axi4_switch2_axi_s_0),
  .bid_axi_s_0          (bid_cpu_mst_axi4_switch2_axi_s_0),
  .bresp_axi_s_0        (bresp_cpu_mst_axi4_switch2_axi_s_0),
  .bvalid_axi_s_0       (bvalid_cpu_mst_axi4_switch2_axi_s_0),
  .bready_axi_s_0       (bready_cpu_mst_axi4_switch2_axi_s_0),
  .arid_axi_s_0         (arid_cpu_mst_axi4_switch2_axi_s_0),
  .araddr_axi_s_0       (araddr_cpu_mst_axi4_switch2_axi_s_0),
  .arlen_axi_s_0        (arlen_cpu_mst_axi4_switch2_axi_s_0),
  .arsize_axi_s_0       (arsize_cpu_mst_axi4_switch2_axi_s_0),
  .arburst_axi_s_0      (arburst_cpu_mst_axi4_switch2_axi_s_0),
  .arlock_axi_s_0       (arlock_cpu_mst_axi4_switch2_axi_s_0),
  .arcache_axi_s_0      (arcache_cpu_mst_axi4_switch2_axi_s_0),
  .arprot_axi_s_0       (arprot_cpu_mst_axi4_switch2_axi_s_0),
  .arregion_axi_s_0     (arregion_cpu_mst_axi4_switch2_axi_s_0),
  .arvalid_axi_s_0      (arvalid_cpu_mst_axi4_switch2_axi_s_0),
  .arvalid_vect_axi_s_0 (arvalid_vect_cpu_mst_axi4_switch2_axi_s_0),
  .arready_axi_s_0      (arready_cpu_mst_axi4_switch2_axi_s_0),
  .rid_axi_s_0          (rid_cpu_mst_axi4_switch2_axi_s_0),
  .rdata_axi_s_0        (rdata_cpu_mst_axi4_switch2_axi_s_0),
  .rresp_axi_s_0        (rresp_cpu_mst_axi4_switch2_axi_s_0),
  .rlast_axi_s_0        (rlast_cpu_mst_axi4_switch2_axi_s_0),
  .rvalid_axi_s_0       (rvalid_cpu_mst_axi4_switch2_axi_s_0),
  .rready_axi_s_0       (rready_cpu_mst_axi4_switch2_axi_s_0),
  .aw_qv_axi_s_0        (awqv_cpu_mst_axi4_switch2_axi_s_0),
  .ar_qv_axi_s_0        (arqv_cpu_mst_axi4_switch2_axi_s_0),
  .awid_axi_s_1         (awid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awaddr_axi_s_1       (awaddr_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awlen_axi_s_1        (awlen_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awsize_axi_s_1       (awsize_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awburst_axi_s_1      (awburst_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awlock_axi_s_1       (awlock_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awcache_axi_s_1      (awcache_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awprot_axi_s_1       (awprot_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awregion_axi_s_1     (awregion_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awvalid_axi_s_1      (awvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awvalid_vect_axi_s_1 (awvalid_vect_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awready_axi_s_1      (awready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wdata_axi_s_1        (wdata_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wstrb_axi_s_1        (wstrb_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wlast_axi_s_1        (wlast_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wvalid_axi_s_1       (wvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wready_axi_s_1       (wready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bid_axi_s_1          (bid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bresp_axi_s_1        (bresp_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bvalid_axi_s_1       (bvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bready_axi_s_1       (bready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arid_axi_s_1         (arid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .araddr_axi_s_1       (araddr_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arlen_axi_s_1        (arlen_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arsize_axi_s_1       (arsize_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arburst_axi_s_1      (arburst_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arlock_axi_s_1       (arlock_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arcache_axi_s_1      (arcache_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arprot_axi_s_1       (arprot_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arregion_axi_s_1     (arregion_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arvalid_axi_s_1      (arvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arvalid_vect_axi_s_1 (arvalid_vect_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arready_axi_s_1      (arready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rid_axi_s_1          (rid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rdata_axi_s_1        (rdata_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rresp_axi_s_1        (rresp_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rlast_axi_s_1        (rlast_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rvalid_axi_s_1       (rvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rready_axi_s_1       (rready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .aw_qv_axi_s_1        (awqv_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .ar_qv_axi_s_1        (arqv_vgalcd_mst_axi4_ib_switch2_axi_s_1)
);


nic400_default_slave_ds_1_ysyx_rv32     u_default_slave_ds_1 (
  .awid                 (awid_switch2_ds_1_axi_s_0),
  .awvalid              (awvalid_switch2_ds_1_axi_s_0),
  .awready              (awready_switch2_ds_1_axi_s_0),
  .wlast                (wlast_switch2_ds_1_axi_s_0),
  .wvalid               (wvalid_switch2_ds_1_axi_s_0),
  .wready               (wready_switch2_ds_1_axi_s_0),
  .bid                  (bid_switch2_ds_1_axi_s_0),
  .bresp                (bresp_switch2_ds_1_axi_s_0),
  .bvalid               (bvalid_switch2_ds_1_axi_s_0),
  .bready               (bready_switch2_ds_1_axi_s_0),
  .arid                 (arid_switch2_ds_1_axi_s_0),
  .arlen                (arlen_switch2_ds_1_axi_s_0),
  .arvalid              (arvalid_switch2_ds_1_axi_s_0),
  .arready              (arready_switch2_ds_1_axi_s_0),
  .rid                  (rid_switch2_ds_1_axi_s_0),
  .rresp                (rresp_switch2_ds_1_axi_s_0),
  .rlast                (rlast_switch2_ds_1_axi_s_0),
  .rvalid               (rvalid_switch2_ds_1_axi_s_0),
  .rready               (rready_switch2_ds_1_axi_s_0),
  .aclk                 (clk_core_200_800mclk),
  .aresetn              (clk_core_200_800mresetn)
);


nic400_ib_chiplink_slv_axi4_tpv_ib_slave_domain_ysyx_rv32     u_ib_chiplink_slv_axi4_tpv_ib_s (
  .awid_axi4_s          (awid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_chiplink_slv_axi4_tpv_ib_axi4_s),
  .aclk_s               (clk_core_200_800mclk),
  .aresetn_s            (clk_core_200_800mresetn),
  .aw_data_async        (aw_data_chiplink_slv_axi4_tpv_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .b_data_async         (b_data_chiplink_slv_axi4_tpv_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .ar_data_async        (ar_data_chiplink_slv_axi4_tpv_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .r_data_async         (r_data_chiplink_slv_axi4_tpv_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .w_data_async         (w_data_chiplink_slv_axi4_tpv_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async)
);


nic400_ib_dma_axi4_cpu_ib_master_domain_ysyx_rv32     u_ib_dma_axi4_cpu_ib_m (
  .awid_axi4_m          (awid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awaddr_axi4_m        (awaddr_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awlen_axi4_m         (awlen_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awsize_axi4_m        (awsize_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awburst_axi4_m       (awburst_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awlock_axi4_m        (awlock_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awcache_axi4_m       (awcache_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awprot_axi4_m        (awprot_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awvalid_axi4_m       (awvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .awready_axi4_m       (awready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wdata_axi4_m         (wdata_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wstrb_axi4_m         (wstrb_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wlast_axi4_m         (wlast_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wvalid_axi4_m        (wvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .wready_axi4_m        (wready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bid_axi4_m           (bid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bresp_axi4_m         (bresp_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bvalid_axi4_m        (bvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .bready_axi4_m        (bready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arid_axi4_m          (arid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .araddr_axi4_m        (araddr_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arlen_axi4_m         (arlen_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arsize_axi4_m        (arsize_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arburst_axi4_m       (arburst_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arlock_axi4_m        (arlock_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arcache_axi4_m       (arcache_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arprot_axi4_m        (arprot_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arvalid_axi4_m       (arvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .arready_axi4_m       (arready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rid_axi4_m           (rid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rdata_axi4_m         (rdata_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rresp_axi4_m         (rresp_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rlast_axi4_m         (rlast_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rvalid_axi4_m        (rvalid_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .rready_axi4_m        (rready_dma_axi4_cpu_ib_dma_axi4_cpu_dma_axi4_cpu_s),
  .aclk_m               (clk_core_200_800mclk),
  .aresetn_m            (clk_core_200_800mresetn),
  .aw_data_async        (aw_data_dma_axi4_cpu_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_dma_axi4_cpu_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_dma_axi4_cpu_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_dma_axi4_cpu_ib_int_async),
  .b_data_async         (b_data_dma_axi4_cpu_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_dma_axi4_cpu_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_dma_axi4_cpu_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_dma_axi4_cpu_ib_int_async),
  .ar_data_async        (ar_data_dma_axi4_cpu_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_dma_axi4_cpu_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_dma_axi4_cpu_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_dma_axi4_cpu_ib_int_async),
  .r_data_async         (r_data_dma_axi4_cpu_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_dma_axi4_cpu_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_dma_axi4_cpu_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_dma_axi4_cpu_ib_int_async),
  .w_data_async         (w_data_dma_axi4_cpu_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_dma_axi4_cpu_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_dma_axi4_cpu_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_dma_axi4_cpu_ib_int_async)
);


nic400_ib_perip0_gp_apb4_ib_slave_domain_ysyx_rv32     u_ib_perip0_gp_apb4_ib_s (
  .awid_axi4_s          (awid_switch2_perip0_gp_apb4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_perip0_gp_apb4_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_perip0_gp_apb4_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_perip0_gp_apb4_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_perip0_gp_apb4_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_perip0_gp_apb4_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_perip0_gp_apb4_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_perip0_gp_apb4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_perip0_gp_apb4_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_perip0_gp_apb4_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_perip0_gp_apb4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_perip0_gp_apb4_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_perip0_gp_apb4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_perip0_gp_apb4_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_perip0_gp_apb4_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_perip0_gp_apb4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_perip0_gp_apb4_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_perip0_gp_apb4_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_perip0_gp_apb4_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_perip0_gp_apb4_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_perip0_gp_apb4_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_perip0_gp_apb4_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_perip0_gp_apb4_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_perip0_gp_apb4_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_perip0_gp_apb4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_perip0_gp_apb4_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_perip0_gp_apb4_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_perip0_gp_apb4_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_perip0_gp_apb4_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_perip0_gp_apb4_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_perip0_gp_apb4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_perip0_gp_apb4_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_perip0_gp_apb4_ib_axi4_s),
  .aclk_s               (clk_core_200_800mclk),
  .aresetn_s            (clk_core_200_800mresetn),
  .a_data_async         (a_data_perip0_gp_apb4_ib_int_async),
  .a_rpntr_gry_async    (a_rpntr_gry_perip0_gp_apb4_ib_int_async),
  .a_rpntr_bin          (a_rpntr_bin_perip0_gp_apb4_ib_int_async),
  .a_wpntr_gry_async    (a_wpntr_gry_perip0_gp_apb4_ib_int_async),
  .d_data_async         (d_data_perip0_gp_apb4_ib_int_async),
  .d_rpntr_gry_async    (d_rpntr_gry_perip0_gp_apb4_ib_int_async),
  .d_rpntr_bin          (d_rpntr_bin_perip0_gp_apb4_ib_int_async),
  .d_wpntr_gry_async    (d_wpntr_gry_perip0_gp_apb4_ib_int_async),
  .w_data_async         (w_data_perip0_gp_apb4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_perip0_gp_apb4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_perip0_gp_apb4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_perip0_gp_apb4_ib_int_async)
);


nic400_ib_perip1_gp_apb4_ib_slave_domain_ysyx_rv32     u_ib_perip1_gp_apb4_ib_s (
  .awid_axi4_s          (awid_switch2_perip1_gp_apb4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_perip1_gp_apb4_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_perip1_gp_apb4_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_perip1_gp_apb4_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_perip1_gp_apb4_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_perip1_gp_apb4_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_perip1_gp_apb4_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_perip1_gp_apb4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_perip1_gp_apb4_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_perip1_gp_apb4_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_perip1_gp_apb4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_perip1_gp_apb4_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_perip1_gp_apb4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_perip1_gp_apb4_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_perip1_gp_apb4_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_perip1_gp_apb4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_perip1_gp_apb4_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_perip1_gp_apb4_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_perip1_gp_apb4_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_perip1_gp_apb4_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_perip1_gp_apb4_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_perip1_gp_apb4_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_perip1_gp_apb4_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_perip1_gp_apb4_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_perip1_gp_apb4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_perip1_gp_apb4_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_perip1_gp_apb4_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_perip1_gp_apb4_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_perip1_gp_apb4_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_perip1_gp_apb4_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_perip1_gp_apb4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_perip1_gp_apb4_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_perip1_gp_apb4_ib_axi4_s),
  .aclk_s               (clk_core_200_800mclk),
  .aresetn_s            (clk_core_200_800mresetn),
  .a_data_async         (a_data_perip1_gp_apb4_ib_int_async),
  .a_rpntr_gry_async    (a_rpntr_gry_perip1_gp_apb4_ib_int_async),
  .a_rpntr_bin          (a_rpntr_bin_perip1_gp_apb4_ib_int_async),
  .a_wpntr_gry_async    (a_wpntr_gry_perip1_gp_apb4_ib_int_async),
  .d_data_async         (d_data_perip1_gp_apb4_ib_int_async),
  .d_rpntr_gry_async    (d_rpntr_gry_perip1_gp_apb4_ib_int_async),
  .d_rpntr_bin          (d_rpntr_bin_perip1_gp_apb4_ib_int_async),
  .d_wpntr_gry_async    (d_wpntr_gry_perip1_gp_apb4_ib_int_async),
  .w_data_async         (w_data_perip1_gp_apb4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_perip1_gp_apb4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_perip1_gp_apb4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_perip1_gp_apb4_ib_int_async)
);


nic400_ib_psram_slv_axi4_ib_slave_domain_ysyx_rv32     u_ib_psram_slv_axi4_ib_s (
  .awid_axi4_s          (awid_switch2_psram_slv_axi4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_psram_slv_axi4_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_psram_slv_axi4_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_psram_slv_axi4_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_psram_slv_axi4_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_psram_slv_axi4_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_psram_slv_axi4_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_psram_slv_axi4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_psram_slv_axi4_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_psram_slv_axi4_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_psram_slv_axi4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_psram_slv_axi4_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_psram_slv_axi4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_psram_slv_axi4_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_psram_slv_axi4_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_psram_slv_axi4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_psram_slv_axi4_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_psram_slv_axi4_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_psram_slv_axi4_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_psram_slv_axi4_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_psram_slv_axi4_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_psram_slv_axi4_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_psram_slv_axi4_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_psram_slv_axi4_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_psram_slv_axi4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_psram_slv_axi4_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_psram_slv_axi4_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_psram_slv_axi4_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_psram_slv_axi4_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_psram_slv_axi4_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_psram_slv_axi4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_psram_slv_axi4_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_psram_slv_axi4_ib_axi4_s),
  .aclk_s               (clk_core_200_800mclk),
  .aresetn_s            (clk_core_200_800mresetn),
  .aw_data_async        (aw_data_psram_slv_axi4_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_psram_slv_axi4_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_psram_slv_axi4_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_psram_slv_axi4_ib_int_async),
  .b_data_async         (b_data_psram_slv_axi4_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_psram_slv_axi4_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_psram_slv_axi4_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_psram_slv_axi4_ib_int_async),
  .ar_data_async        (ar_data_psram_slv_axi4_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_psram_slv_axi4_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_psram_slv_axi4_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_psram_slv_axi4_ib_int_async),
  .r_data_async         (r_data_psram_slv_axi4_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_psram_slv_axi4_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_psram_slv_axi4_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_psram_slv_axi4_ib_int_async),
  .w_data_async         (w_data_psram_slv_axi4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_psram_slv_axi4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_psram_slv_axi4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_psram_slv_axi4_ib_int_async)
);


nic400_ib_sdram_slv_axi4_ib_slave_domain_ysyx_rv32     u_ib_sdram_slv_axi4_ib_s (
  .awid_axi4_s          (awid_switch2_sdram_slv_axi4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_sdram_slv_axi4_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_sdram_slv_axi4_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_sdram_slv_axi4_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_sdram_slv_axi4_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_sdram_slv_axi4_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_sdram_slv_axi4_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_sdram_slv_axi4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_sdram_slv_axi4_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_sdram_slv_axi4_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_sdram_slv_axi4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_sdram_slv_axi4_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_sdram_slv_axi4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_sdram_slv_axi4_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_sdram_slv_axi4_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_sdram_slv_axi4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_sdram_slv_axi4_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_sdram_slv_axi4_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_sdram_slv_axi4_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_sdram_slv_axi4_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_sdram_slv_axi4_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_sdram_slv_axi4_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_sdram_slv_axi4_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_sdram_slv_axi4_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_sdram_slv_axi4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_sdram_slv_axi4_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_sdram_slv_axi4_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_sdram_slv_axi4_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_sdram_slv_axi4_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_sdram_slv_axi4_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_sdram_slv_axi4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_sdram_slv_axi4_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_sdram_slv_axi4_ib_axi4_s),
  .aclk_s               (clk_core_200_800mclk),
  .aresetn_s            (clk_core_200_800mresetn),
  .aw_data_async        (aw_data_sdram_slv_axi4_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .b_data_async         (b_data_sdram_slv_axi4_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .ar_data_async        (ar_data_sdram_slv_axi4_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .r_data_async         (r_data_sdram_slv_axi4_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .w_data_async         (w_data_sdram_slv_axi4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_sdram_slv_axi4_ib_int_async)
);


nic400_ib_sram_slv_axi4_ib_master_domain_ysyx_rv32     u_ib_sram_slv_axi4_ib_m (
  .awid_axi4_m          (awid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awaddr_axi4_m        (awaddr_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awlen_axi4_m         (awlen_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awsize_axi4_m        (awsize_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awburst_axi4_m       (awburst_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awlock_axi4_m        (awlock_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awcache_axi4_m       (awcache_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awprot_axi4_m        (awprot_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awvalid_axi4_m       (awvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .awregion_axi4_m      (),
  .awready_axi4_m       (awready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wdata_axi4_m         (wdata_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wstrb_axi4_m         (wstrb_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wlast_axi4_m         (wlast_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wvalid_axi4_m        (wvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .wready_axi4_m        (wready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bid_axi4_m           (bid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bresp_axi4_m         (bresp_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bvalid_axi4_m        (bvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .bready_axi4_m        (bready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arid_axi4_m          (arid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .araddr_axi4_m        (araddr_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arlen_axi4_m         (arlen_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arsize_axi4_m        (arsize_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arburst_axi4_m       (arburst_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arlock_axi4_m        (arlock_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arcache_axi4_m       (arcache_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arprot_axi4_m        (arprot_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arvalid_axi4_m       (arvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .arregion_axi4_m      (),
  .arready_axi4_m       (arready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rid_axi4_m           (rid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rdata_axi4_m         (rdata_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rresp_axi4_m         (rresp_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rlast_axi4_m         (rlast_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rvalid_axi4_m        (rvalid_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .rready_axi4_m        (rready_sram_slv_axi4_ib_sram_slv_axi4_sram_slv_axi4_s),
  .aclk                 (clk_core_200_800mclk),
  .aresetn              (clk_core_200_800mresetn),
  .aw_data              (aw_data_sram_slv_axi4_ib_int),
  .aw_valid             (aw_valid_sram_slv_axi4_ib_int),
  .aw_ready             (aw_ready_sram_slv_axi4_ib_int),
  .b_data               (b_data_sram_slv_axi4_ib_int),
  .b_valid              (b_valid_sram_slv_axi4_ib_int),
  .b_ready              (b_ready_sram_slv_axi4_ib_int),
  .ar_data              (ar_data_sram_slv_axi4_ib_int),
  .ar_valid             (ar_valid_sram_slv_axi4_ib_int),
  .ar_ready             (ar_ready_sram_slv_axi4_ib_int),
  .r_data               (r_data_sram_slv_axi4_ib_int),
  .r_valid              (r_valid_sram_slv_axi4_ib_int),
  .r_ready              (r_ready_sram_slv_axi4_ib_int),
  .w_data               (w_data_sram_slv_axi4_ib_int),
  .w_valid              (w_valid_sram_slv_axi4_ib_int),
  .w_ready              (w_ready_sram_slv_axi4_ib_int)
);


nic400_ib_sram_slv_axi4_ib_slave_domain_ysyx_rv32     u_ib_sram_slv_axi4_ib_s (
  .awid_axi4_s          (awid_switch2_sram_slv_axi4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_sram_slv_axi4_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_sram_slv_axi4_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_sram_slv_axi4_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_sram_slv_axi4_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_sram_slv_axi4_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_sram_slv_axi4_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_sram_slv_axi4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_sram_slv_axi4_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_sram_slv_axi4_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_sram_slv_axi4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_sram_slv_axi4_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_sram_slv_axi4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_sram_slv_axi4_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_sram_slv_axi4_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_sram_slv_axi4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_sram_slv_axi4_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_sram_slv_axi4_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_sram_slv_axi4_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_sram_slv_axi4_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_sram_slv_axi4_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_sram_slv_axi4_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_sram_slv_axi4_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_sram_slv_axi4_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_sram_slv_axi4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_sram_slv_axi4_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_sram_slv_axi4_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_sram_slv_axi4_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_sram_slv_axi4_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_sram_slv_axi4_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_sram_slv_axi4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_sram_slv_axi4_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_sram_slv_axi4_ib_axi4_s),
  .aclk                 (clk_core_200_800mclk),
  .aresetn              (clk_core_200_800mresetn),
  .aw_data              (aw_data_sram_slv_axi4_ib_int),
  .aw_valid             (aw_valid_sram_slv_axi4_ib_int),
  .aw_ready             (aw_ready_sram_slv_axi4_ib_int),
  .b_data               (b_data_sram_slv_axi4_ib_int),
  .b_valid              (b_valid_sram_slv_axi4_ib_int),
  .b_ready              (b_ready_sram_slv_axi4_ib_int),
  .ar_data              (ar_data_sram_slv_axi4_ib_int),
  .ar_valid             (ar_valid_sram_slv_axi4_ib_int),
  .ar_ready             (ar_ready_sram_slv_axi4_ib_int),
  .r_data               (r_data_sram_slv_axi4_ib_int),
  .r_valid              (r_valid_sram_slv_axi4_ib_int),
  .r_ready              (r_ready_sram_slv_axi4_ib_int),
  .w_data               (w_data_sram_slv_axi4_ib_int),
  .w_valid              (w_valid_sram_slv_axi4_ib_int),
  .w_ready              (w_ready_sram_slv_axi4_ib_int)
);


nic400_ib_sys_gp_apb4_ib_slave_domain_ysyx_rv32     u_ib_sys_gp_apb4_ib_s (
  .awid_axi4_s          (awid_switch2_sys_gp_apb4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_sys_gp_apb4_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_sys_gp_apb4_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_sys_gp_apb4_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_sys_gp_apb4_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_sys_gp_apb4_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_sys_gp_apb4_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_sys_gp_apb4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_sys_gp_apb4_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_sys_gp_apb4_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_sys_gp_apb4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_sys_gp_apb4_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_sys_gp_apb4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_sys_gp_apb4_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_sys_gp_apb4_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_sys_gp_apb4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_sys_gp_apb4_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_sys_gp_apb4_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_sys_gp_apb4_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_sys_gp_apb4_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_sys_gp_apb4_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_sys_gp_apb4_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_sys_gp_apb4_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_sys_gp_apb4_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_sys_gp_apb4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_sys_gp_apb4_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_sys_gp_apb4_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_sys_gp_apb4_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_sys_gp_apb4_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_sys_gp_apb4_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_sys_gp_apb4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_sys_gp_apb4_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_sys_gp_apb4_ib_axi4_s),
  .aclk_s               (clk_core_200_800mclk),
  .aresetn_s            (clk_core_200_800mresetn),
  .a_data_async         (a_data_sys_gp_apb4_ib_int_async),
  .a_rpntr_gry_async    (a_rpntr_gry_sys_gp_apb4_ib_int_async),
  .a_rpntr_bin          (a_rpntr_bin_sys_gp_apb4_ib_int_async),
  .a_wpntr_gry_async    (a_wpntr_gry_sys_gp_apb4_ib_int_async),
  .d_data_async         (d_data_sys_gp_apb4_ib_int_async),
  .d_rpntr_gry_async    (d_rpntr_gry_sys_gp_apb4_ib_int_async),
  .d_rpntr_bin          (d_rpntr_bin_sys_gp_apb4_ib_int_async),
  .d_wpntr_gry_async    (d_wpntr_gry_sys_gp_apb4_ib_int_async),
  .w_data_async         (w_data_sys_gp_apb4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_sys_gp_apb4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_sys_gp_apb4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_sys_gp_apb4_ib_int_async)
);


nic400_ib_tpv_gp_apb4_ib_slave_domain_ysyx_rv32     u_ib_tpv_gp_apb4_ib_s (
  .awid_axi4_s          (awid_switch2_tpv_gp_apb4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_switch2_tpv_gp_apb4_ib_axi4_s),
  .awlen_axi4_s         (awlen_switch2_tpv_gp_apb4_ib_axi4_s),
  .awsize_axi4_s        (awsize_switch2_tpv_gp_apb4_ib_axi4_s),
  .awburst_axi4_s       (awburst_switch2_tpv_gp_apb4_ib_axi4_s),
  .awlock_axi4_s        (awlock_switch2_tpv_gp_apb4_ib_axi4_s),
  .awcache_axi4_s       (awcache_switch2_tpv_gp_apb4_ib_axi4_s),
  .awprot_axi4_s        (awprot_switch2_tpv_gp_apb4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .awregion_axi4_s      (awregion_switch2_tpv_gp_apb4_ib_axi4_s),
  .awready_axi4_s       (awready_switch2_tpv_gp_apb4_ib_axi4_s),
  .wdata_axi4_s         (wdata_switch2_tpv_gp_apb4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_switch2_tpv_gp_apb4_ib_axi4_s),
  .wlast_axi4_s         (wlast_switch2_tpv_gp_apb4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .wready_axi4_s        (wready_switch2_tpv_gp_apb4_ib_axi4_s),
  .bid_axi4_s           (bid_switch2_tpv_gp_apb4_ib_axi4_s),
  .bresp_axi4_s         (bresp_switch2_tpv_gp_apb4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .bready_axi4_s        (bready_switch2_tpv_gp_apb4_ib_axi4_s),
  .arid_axi4_s          (arid_switch2_tpv_gp_apb4_ib_axi4_s),
  .araddr_axi4_s        (araddr_switch2_tpv_gp_apb4_ib_axi4_s),
  .arlen_axi4_s         (arlen_switch2_tpv_gp_apb4_ib_axi4_s),
  .arsize_axi4_s        (arsize_switch2_tpv_gp_apb4_ib_axi4_s),
  .arburst_axi4_s       (arburst_switch2_tpv_gp_apb4_ib_axi4_s),
  .arlock_axi4_s        (arlock_switch2_tpv_gp_apb4_ib_axi4_s),
  .arcache_axi4_s       (arcache_switch2_tpv_gp_apb4_ib_axi4_s),
  .arprot_axi4_s        (arprot_switch2_tpv_gp_apb4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .arregion_axi4_s      (arregion_switch2_tpv_gp_apb4_ib_axi4_s),
  .arready_axi4_s       (arready_switch2_tpv_gp_apb4_ib_axi4_s),
  .rid_axi4_s           (rid_switch2_tpv_gp_apb4_ib_axi4_s),
  .rdata_axi4_s         (rdata_switch2_tpv_gp_apb4_ib_axi4_s),
  .rresp_axi4_s         (rresp_switch2_tpv_gp_apb4_ib_axi4_s),
  .rlast_axi4_s         (rlast_switch2_tpv_gp_apb4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_switch2_tpv_gp_apb4_ib_axi4_s),
  .rready_axi4_s        (rready_switch2_tpv_gp_apb4_ib_axi4_s),
  .aclk_s               (clk_core_200_800mclk),
  .aresetn_s            (clk_core_200_800mresetn),
  .a_data_async         (a_data_tpv_gp_apb4_ib_int_async),
  .a_rpntr_gry_async    (a_rpntr_gry_tpv_gp_apb4_ib_int_async),
  .a_rpntr_bin          (a_rpntr_bin_tpv_gp_apb4_ib_int_async),
  .a_wpntr_gry_async    (a_wpntr_gry_tpv_gp_apb4_ib_int_async),
  .d_data_async         (d_data_tpv_gp_apb4_ib_int_async),
  .d_rpntr_gry_async    (d_rpntr_gry_tpv_gp_apb4_ib_int_async),
  .d_rpntr_bin          (d_rpntr_bin_tpv_gp_apb4_ib_int_async),
  .d_wpntr_gry_async    (d_wpntr_gry_tpv_gp_apb4_ib_int_async),
  .w_data_async         (w_data_tpv_gp_apb4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_tpv_gp_apb4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_tpv_gp_apb4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_tpv_gp_apb4_ib_int_async)
);


nic400_ib_vgalcd_mst_axi4_ib_master_domain_ysyx_rv32     u_ib_vgalcd_mst_axi4_ib_m (
  .awid_axi4_m          (awid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awaddr_axi4_m        (awaddr_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awlen_axi4_m         (awlen_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awsize_axi4_m        (awsize_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awburst_axi4_m       (awburst_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awlock_axi4_m        (awlock_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awcache_axi4_m       (awcache_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awprot_axi4_m        (awprot_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awvalid_axi4_m       (awvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awvalid_vect_axi4_m  (awvalid_vect_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awregion_axi4_m      (awregion_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awready_axi4_m       (awready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wdata_axi4_m         (wdata_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wstrb_axi4_m         (wstrb_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wlast_axi4_m         (wlast_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wvalid_axi4_m        (wvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .wready_axi4_m        (wready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bid_axi4_m           (bid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bresp_axi4_m         (bresp_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bvalid_axi4_m        (bvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .bready_axi4_m        (bready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arid_axi4_m          (arid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .araddr_axi4_m        (araddr_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arlen_axi4_m         (arlen_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arsize_axi4_m        (arsize_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arburst_axi4_m       (arburst_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arlock_axi4_m        (arlock_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arcache_axi4_m       (arcache_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arprot_axi4_m        (arprot_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arvalid_axi4_m       (arvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arvalid_vect_axi4_m  (arvalid_vect_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arregion_axi4_m      (arregion_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arready_axi4_m       (arready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rid_axi4_m           (rid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rdata_axi4_m         (rdata_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rresp_axi4_m         (rresp_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rlast_axi4_m         (rlast_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rvalid_axi4_m        (rvalid_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .rready_axi4_m        (rready_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .awqv_axi4_m          (awqv_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .arqv_axi4_m          (arqv_vgalcd_mst_axi4_ib_switch2_axi_s_1),
  .aclk_m               (clk_core_200_800mclk),
  .aresetn_m            (clk_core_200_800mresetn),
  .aw_data_async        (aw_data_vgalcd_mst_axi4_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .b_data_async         (b_data_vgalcd_mst_axi4_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .ar_data_async        (ar_data_vgalcd_mst_axi4_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .r_data_async         (r_data_vgalcd_mst_axi4_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .w_data_async         (w_data_vgalcd_mst_axi4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_vgalcd_mst_axi4_ib_int_async)
);



endmodule
